Group : test::ral_reg_CH0_CSR::cg_bits

===============================================================================
Group : test::ral_reg_CH0_CSR::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 24.40  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME         
 25.00 1      100    1        64           64            CH0_CSR_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CH0_CSR::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      24.40   


Variables for Group  test::ral_reg_CH0_CSR::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  1      1        0                    
DST_SEL  4        3         1       25.00   100  1      1        0                    
SRC_SEL  4        3         1       25.00   100  1      1        0                    
INC_DST  4        3         1       25.00   100  1      1        0                    
INC_SRC  4        3         1       25.00   100  1      1        0                    
MODE     4        3         1       25.00   100  1      1        0                    
ARS      4        3         1       25.00   100  1      1        0                    
USE_ED   4        3         1       25.00   100  1      1        0                    
SZ_WB    4        3         1       25.00   100  1      1        0                    
STOP     2        2         0       0.00    100  1      1        0                    
BUSY     3        2         1       33.33   100  1      1        0                    
DONE     3        2         1       33.33   100  1      1        0                    
ERR      4        3         1       25.00   100  1      1        0                    
PARITY   12       9         3       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : CH0_CSR_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CH0_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   CH0_CSR_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  CH0_CSR_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


Group : test::ral_reg_CHN_CSR::cg_bits

===============================================================================
Group : test::ral_reg_CHN_CSR::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 24.40  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

30 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME          
 25.00 1      100    1        64           64            ch30_csr_bits 
 25.00 1      100    1        64           64            ch29_csr_bits 
 25.00 1      100    1        64           64            ch28_csr_bits 
 25.00 1      100    1        64           64            ch27_csr_bits 
 25.00 1      100    1        64           64            ch26_csr_bits 
 25.00 1      100    1        64           64            ch25_csr_bits 
 25.00 1      100    1        64           64            ch24_csr_bits 
 25.00 1      100    1        64           64            ch23_csr_bits 
 25.00 1      100    1        64           64            ch22_csr_bits 
 25.00 1      100    1        64           64            ch21_csr_bits 
 25.00 1      100    1        64           64            ch20_csr_bits 
 25.00 1      100    1        64           64            ch19_csr_bits 
 25.00 1      100    1        64           64            ch18_csr_bits 
 25.00 1      100    1        64           64            ch17_csr_bits 
 25.00 1      100    1        64           64            ch16_csr_bits 
 25.00 1      100    1        64           64            ch15_csr_bits 
 25.00 1      100    1        64           64            ch14_csr_bits 
 25.00 1      100    1        64           64            ch13_csr_bits 
 25.00 1      100    1        64           64            ch12_csr_bits 
 25.00 1      100    1        64           64            ch11_csr_bits 
 25.00 1      100    1        64           64            ch10_csr_bits 
 25.00 1      100    1        64           64            ch9_csr_bits  
 25.00 1      100    1        64           64            ch8_csr_bits  
 25.00 1      100    1        64           64            ch7_csr_bits  
 25.00 1      100    1        64           64            ch6_csr_bits  
 25.00 1      100    1        64           64            ch5_csr_bits  
 25.00 1      100    1        64           64            ch4_csr_bits  
 25.00 1      100    1        64           64            ch3_csr_bits  
 25.00 1      100    1        64           64            ch2_csr_bits  
 25.00 1      100    1        64           64            ch1_csr_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_CSR::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      24.40   


Variables for Group  test::ral_reg_CHN_CSR::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  1      1        0                    
DST_SEL  4        3         1       25.00   100  1      1        0                    
SRC_SEL  4        3         1       25.00   100  1      1        0                    
INC_DST  4        3         1       25.00   100  1      1        0                    
INC_SRC  4        3         1       25.00   100  1      1        0                    
MODE     4        3         1       25.00   100  1      1        0                    
ARS      4        3         1       25.00   100  1      1        0                    
USE_ED   4        3         1       25.00   100  1      1        0                    
SZ_WB    4        3         1       25.00   100  1      1        0                    
STOP     2        2         0       0.00    100  1      1        0                    
BUSY     3        2         1       33.33   100  1      1        0                    
DONE     3        2         1       33.33   100  1      1        0                    
ERR      4        3         1       25.00   100  1      1        0                    
PARITY   12       9         3       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 1020  1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 1020  1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 1020  1        
bit_1_rd_as_0 1020  1        
bit_0_rd_as_0 1020  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch30_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch29_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch28_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch27_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch26_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch25_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch24_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch23_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch22_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch21_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch20_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch19_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch18_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch17_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch16_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch15_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch14_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch13_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch12_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch11_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch10_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch9_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch8_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch7_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch6_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch5_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch4_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch3_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch2_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_csr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 24.40  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_csr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 60       45        15      25.00   


Variables for Group Instance  ch1_csr_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CH_EN    4        3         1       25.00   100  4      1        0                    
DST_SEL  4        3         1       25.00   100  4      1        0                    
SRC_SEL  4        3         1       25.00   100  4      1        0                    
INC_DST  4        3         1       25.00   100  4      1        0                    
INC_SRC  4        3         1       25.00   100  4      1        0                    
MODE     4        3         1       25.00   100  4      1        0                    
ARS      4        3         1       25.00   100  4      1        0                    
USE_ED   4        3         1       25.00   100  4      1        0                    
SZ_WB    4        3         1       25.00   100  4      1        0                    
STOP     2        2         0       0.00    100  2      1        0                    
BUSY     3        2         1       33.33   100  3      1        0                    
DONE     3        2         1       33.33   100  3      1        0                    
ERR      4        3         1       25.00   100  4      1        0                    
PARITY   12       9         3       25.00   100  12     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CH_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for CH_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable DST_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for DST_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SRC_SEL


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SRC_SEL


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_DST


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_DST


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable INC_SRC


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for INC_SRC


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable MODE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for MODE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable ARS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ARS


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable USE_ED


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for USE_ED


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable SZ_WB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SZ_WB


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable STOP


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 2        2         0       0.00    


User Defined Bins for STOP


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


-------------------------------------------------------------------------------

Summary for Variable BUSY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for BUSY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable DONE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        2         1       33.33   


User Defined Bins for DONE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME     COUNT AT LEAST 
bit_0_rd 34    1        


-------------------------------------------------------------------------------

Summary for Variable ERR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for ERR


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable PARITY


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 12       9         3       25.00   


User Defined Bins for PARITY


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_2_rd_as_1 0     1        1      
bit_2_wr_as_1 0     1        1      
bit_2_wr_as_0 0     1        1      
bit_1_rd_as_1 0     1        1      
bit_1_wr_as_1 0     1        1      
bit_1_wr_as_0 0     1        1      
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_2_rd_as_0 34    1        
bit_1_rd_as_0 34    1        
bit_0_rd_as_0 34    1        


Group : test::ral_reg_CSR::cg_bits

===============================================================================
Group : test::ral_reg_CSR::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME     
 25.00 1      100    1        64           64            CSR_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CSR::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 4        3         1       25.00   


Variables for Group  test::ral_reg_CSR::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
PAUSE    4        3         1       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable PAUSE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for PAUSE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : CSR_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                       
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CSR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   CSR_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 4        3         1       25.00   


Variables for Group Instance  CSR_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
PAUSE    4        3         1       25.00   100  4      1        0                    


-------------------------------------------------------------------------------

Summary for Variable PAUSE


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for PAUSE


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


Group : test::ral_reg_INT_MASKA::cg_bits

===============================================================================
Group : test::ral_reg_INT_MASKA::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME           
 25.00 1      100    1        64           64            INT_MASKA_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_INT_MASKA::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group  test::ral_reg_INT_MASKA::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  1      1        0                    
f_mask1  4        3         1       25.00   100  1      1        0                    
f_mask2  4        3         1       25.00   100  1      1        0                    
f_mask3  4        3         1       25.00   100  1      1        0                    
f_mask4  4        3         1       25.00   100  1      1        0                    
f_mask5  4        3         1       25.00   100  1      1        0                    
f_mask6  4        3         1       25.00   100  1      1        0                    
f_mask7  4        3         1       25.00   100  1      1        0                    
f_mask8  4        3         1       25.00   100  1      1        0                    
f_mask9  4        3         1       25.00   100  1      1        0                    
f_mask10 4        3         1       25.00   100  1      1        0                    
f_mask11 4        3         1       25.00   100  1      1        0                    
f_mask12 4        3         1       25.00   100  1      1        0                    
f_mask13 4        3         1       25.00   100  1      1        0                    
f_mask14 4        3         1       25.00   100  1      1        0                    
f_mask15 4        3         1       25.00   100  1      1        0                    
f_mask16 4        3         1       25.00   100  1      1        0                    
f_mask17 4        3         1       25.00   100  1      1        0                    
f_mask18 4        3         1       25.00   100  1      1        0                    
f_mask19 4        3         1       25.00   100  1      1        0                    
f_mask20 4        3         1       25.00   100  1      1        0                    
f_mask21 4        3         1       25.00   100  1      1        0                    
f_mask22 4        3         1       25.00   100  1      1        0                    
f_mask23 4        3         1       25.00   100  1      1        0                    
f_mask24 4        3         1       25.00   100  1      1        0                    
f_mask25 4        3         1       25.00   100  1      1        0                    
f_mask26 4        3         1       25.00   100  1      1        0                    
f_mask27 4        3         1       25.00   100  1      1        0                    
f_mask28 4        3         1       25.00   100  1      1        0                    
f_mask29 4        3         1       25.00   100  1      1        0                    
f_mask30 4        3         1       25.00   100  1      1        0                    
f_mask31 4        3         1       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : INT_MASKA_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_INT_MASKA::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   INT_MASKA_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group Instance  INT_MASKA_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  4      1        0                    
f_mask1  4        3         1       25.00   100  4      1        0                    
f_mask2  4        3         1       25.00   100  4      1        0                    
f_mask3  4        3         1       25.00   100  4      1        0                    
f_mask4  4        3         1       25.00   100  4      1        0                    
f_mask5  4        3         1       25.00   100  4      1        0                    
f_mask6  4        3         1       25.00   100  4      1        0                    
f_mask7  4        3         1       25.00   100  4      1        0                    
f_mask8  4        3         1       25.00   100  4      1        0                    
f_mask9  4        3         1       25.00   100  4      1        0                    
f_mask10 4        3         1       25.00   100  4      1        0                    
f_mask11 4        3         1       25.00   100  4      1        0                    
f_mask12 4        3         1       25.00   100  4      1        0                    
f_mask13 4        3         1       25.00   100  4      1        0                    
f_mask14 4        3         1       25.00   100  4      1        0                    
f_mask15 4        3         1       25.00   100  4      1        0                    
f_mask16 4        3         1       25.00   100  4      1        0                    
f_mask17 4        3         1       25.00   100  4      1        0                    
f_mask18 4        3         1       25.00   100  4      1        0                    
f_mask19 4        3         1       25.00   100  4      1        0                    
f_mask20 4        3         1       25.00   100  4      1        0                    
f_mask21 4        3         1       25.00   100  4      1        0                    
f_mask22 4        3         1       25.00   100  4      1        0                    
f_mask23 4        3         1       25.00   100  4      1        0                    
f_mask24 4        3         1       25.00   100  4      1        0                    
f_mask25 4        3         1       25.00   100  4      1        0                    
f_mask26 4        3         1       25.00   100  4      1        0                    
f_mask27 4        3         1       25.00   100  4      1        0                    
f_mask28 4        3         1       25.00   100  4      1        0                    
f_mask29 4        3         1       25.00   100  4      1        0                    
f_mask30 4        3         1       25.00   100  4      1        0                    
f_mask31 4        3         1       25.00   100  4      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


Group : test::ral_reg_INT_MASKB::cg_bits

===============================================================================
Group : test::ral_reg_INT_MASKB::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME           
 25.00 1      100    1        64           64            INT_MASKB_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_INT_MASKB::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group  test::ral_reg_INT_MASKB::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  1      1        0                    
f_mask1  4        3         1       25.00   100  1      1        0                    
f_mask2  4        3         1       25.00   100  1      1        0                    
f_mask3  4        3         1       25.00   100  1      1        0                    
f_mask4  4        3         1       25.00   100  1      1        0                    
f_mask5  4        3         1       25.00   100  1      1        0                    
f_mask6  4        3         1       25.00   100  1      1        0                    
f_mask7  4        3         1       25.00   100  1      1        0                    
f_mask8  4        3         1       25.00   100  1      1        0                    
f_mask9  4        3         1       25.00   100  1      1        0                    
f_mask10 4        3         1       25.00   100  1      1        0                    
f_mask11 4        3         1       25.00   100  1      1        0                    
f_mask12 4        3         1       25.00   100  1      1        0                    
f_mask13 4        3         1       25.00   100  1      1        0                    
f_mask14 4        3         1       25.00   100  1      1        0                    
f_mask15 4        3         1       25.00   100  1      1        0                    
f_mask16 4        3         1       25.00   100  1      1        0                    
f_mask17 4        3         1       25.00   100  1      1        0                    
f_mask18 4        3         1       25.00   100  1      1        0                    
f_mask19 4        3         1       25.00   100  1      1        0                    
f_mask20 4        3         1       25.00   100  1      1        0                    
f_mask21 4        3         1       25.00   100  1      1        0                    
f_mask22 4        3         1       25.00   100  1      1        0                    
f_mask23 4        3         1       25.00   100  1      1        0                    
f_mask24 4        3         1       25.00   100  1      1        0                    
f_mask25 4        3         1       25.00   100  1      1        0                    
f_mask26 4        3         1       25.00   100  1      1        0                    
f_mask27 4        3         1       25.00   100  1      1        0                    
f_mask28 4        3         1       25.00   100  1      1        0                    
f_mask29 4        3         1       25.00   100  1      1        0                    
f_mask30 4        3         1       25.00   100  1      1        0                    
f_mask31 4        3         1       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : INT_MASKB_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_INT_MASKB::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   INT_MASKB_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group Instance  INT_MASKB_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  4      1        0                    
f_mask1  4        3         1       25.00   100  4      1        0                    
f_mask2  4        3         1       25.00   100  4      1        0                    
f_mask3  4        3         1       25.00   100  4      1        0                    
f_mask4  4        3         1       25.00   100  4      1        0                    
f_mask5  4        3         1       25.00   100  4      1        0                    
f_mask6  4        3         1       25.00   100  4      1        0                    
f_mask7  4        3         1       25.00   100  4      1        0                    
f_mask8  4        3         1       25.00   100  4      1        0                    
f_mask9  4        3         1       25.00   100  4      1        0                    
f_mask10 4        3         1       25.00   100  4      1        0                    
f_mask11 4        3         1       25.00   100  4      1        0                    
f_mask12 4        3         1       25.00   100  4      1        0                    
f_mask13 4        3         1       25.00   100  4      1        0                    
f_mask14 4        3         1       25.00   100  4      1        0                    
f_mask15 4        3         1       25.00   100  4      1        0                    
f_mask16 4        3         1       25.00   100  4      1        0                    
f_mask17 4        3         1       25.00   100  4      1        0                    
f_mask18 4        3         1       25.00   100  4      1        0                    
f_mask19 4        3         1       25.00   100  4      1        0                    
f_mask20 4        3         1       25.00   100  4      1        0                    
f_mask21 4        3         1       25.00   100  4      1        0                    
f_mask22 4        3         1       25.00   100  4      1        0                    
f_mask23 4        3         1       25.00   100  4      1        0                    
f_mask24 4        3         1       25.00   100  4      1        0                    
f_mask25 4        3         1       25.00   100  4      1        0                    
f_mask26 4        3         1       25.00   100  4      1        0                    
f_mask27 4        3         1       25.00   100  4      1        0                    
f_mask28 4        3         1       25.00   100  4      1        0                    
f_mask29 4        3         1       25.00   100  4      1        0                    
f_mask30 4        3         1       25.00   100  4      1        0                    
f_mask31 4        3         1       25.00   100  4      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


Group : test::ral_reg_INT_SRCA::cg_bits

===============================================================================
Group : test::ral_reg_INT_SRCA::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME          
 25.00 1      100    1        64           64            INT_SRCA_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_INT_SRCA::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group  test::ral_reg_INT_SRCA::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  1      1        0                    
f_mask1  4        3         1       25.00   100  1      1        0                    
f_mask2  4        3         1       25.00   100  1      1        0                    
f_mask3  4        3         1       25.00   100  1      1        0                    
f_mask4  4        3         1       25.00   100  1      1        0                    
f_mask5  4        3         1       25.00   100  1      1        0                    
f_mask6  4        3         1       25.00   100  1      1        0                    
f_mask7  4        3         1       25.00   100  1      1        0                    
f_mask8  4        3         1       25.00   100  1      1        0                    
f_mask9  4        3         1       25.00   100  1      1        0                    
f_mask10 4        3         1       25.00   100  1      1        0                    
f_mask11 4        3         1       25.00   100  1      1        0                    
f_mask12 4        3         1       25.00   100  1      1        0                    
f_mask13 4        3         1       25.00   100  1      1        0                    
f_mask14 4        3         1       25.00   100  1      1        0                    
f_mask15 4        3         1       25.00   100  1      1        0                    
f_mask16 4        3         1       25.00   100  1      1        0                    
f_mask17 4        3         1       25.00   100  1      1        0                    
f_mask18 4        3         1       25.00   100  1      1        0                    
f_mask19 4        3         1       25.00   100  1      1        0                    
f_mask20 4        3         1       25.00   100  1      1        0                    
f_mask21 4        3         1       25.00   100  1      1        0                    
f_mask22 4        3         1       25.00   100  1      1        0                    
f_mask23 4        3         1       25.00   100  1      1        0                    
f_mask24 4        3         1       25.00   100  1      1        0                    
f_mask25 4        3         1       25.00   100  1      1        0                    
f_mask26 4        3         1       25.00   100  1      1        0                    
f_mask27 4        3         1       25.00   100  1      1        0                    
f_mask28 4        3         1       25.00   100  1      1        0                    
f_mask29 4        3         1       25.00   100  1      1        0                    
f_mask30 4        3         1       25.00   100  1      1        0                    
f_mask31 4        3         1       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : INT_SRCA_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_INT_SRCA::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   INT_SRCA_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group Instance  INT_SRCA_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  4      1        0                    
f_mask1  4        3         1       25.00   100  4      1        0                    
f_mask2  4        3         1       25.00   100  4      1        0                    
f_mask3  4        3         1       25.00   100  4      1        0                    
f_mask4  4        3         1       25.00   100  4      1        0                    
f_mask5  4        3         1       25.00   100  4      1        0                    
f_mask6  4        3         1       25.00   100  4      1        0                    
f_mask7  4        3         1       25.00   100  4      1        0                    
f_mask8  4        3         1       25.00   100  4      1        0                    
f_mask9  4        3         1       25.00   100  4      1        0                    
f_mask10 4        3         1       25.00   100  4      1        0                    
f_mask11 4        3         1       25.00   100  4      1        0                    
f_mask12 4        3         1       25.00   100  4      1        0                    
f_mask13 4        3         1       25.00   100  4      1        0                    
f_mask14 4        3         1       25.00   100  4      1        0                    
f_mask15 4        3         1       25.00   100  4      1        0                    
f_mask16 4        3         1       25.00   100  4      1        0                    
f_mask17 4        3         1       25.00   100  4      1        0                    
f_mask18 4        3         1       25.00   100  4      1        0                    
f_mask19 4        3         1       25.00   100  4      1        0                    
f_mask20 4        3         1       25.00   100  4      1        0                    
f_mask21 4        3         1       25.00   100  4      1        0                    
f_mask22 4        3         1       25.00   100  4      1        0                    
f_mask23 4        3         1       25.00   100  4      1        0                    
f_mask24 4        3         1       25.00   100  4      1        0                    
f_mask25 4        3         1       25.00   100  4      1        0                    
f_mask26 4        3         1       25.00   100  4      1        0                    
f_mask27 4        3         1       25.00   100  4      1        0                    
f_mask28 4        3         1       25.00   100  4      1        0                    
f_mask29 4        3         1       25.00   100  4      1        0                    
f_mask30 4        3         1       25.00   100  4      1        0                    
f_mask31 4        3         1       25.00   100  4      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


Group : test::ral_reg_INT_SRCB::cg_bits

===============================================================================
Group : test::ral_reg_INT_SRCB::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME          
 25.00 1      100    1        64           64            INT_SRCB_bits 




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_INT_SRCB::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group  test::ral_reg_INT_SRCB::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  1      1        0                    
f_mask1  4        3         1       25.00   100  1      1        0                    
f_mask2  4        3         1       25.00   100  1      1        0                    
f_mask3  4        3         1       25.00   100  1      1        0                    
f_mask4  4        3         1       25.00   100  1      1        0                    
f_mask5  4        3         1       25.00   100  1      1        0                    
f_mask6  4        3         1       25.00   100  1      1        0                    
f_mask7  4        3         1       25.00   100  1      1        0                    
f_mask8  4        3         1       25.00   100  1      1        0                    
f_mask9  4        3         1       25.00   100  1      1        0                    
f_mask10 4        3         1       25.00   100  1      1        0                    
f_mask11 4        3         1       25.00   100  1      1        0                    
f_mask12 4        3         1       25.00   100  1      1        0                    
f_mask13 4        3         1       25.00   100  1      1        0                    
f_mask14 4        3         1       25.00   100  1      1        0                    
f_mask15 4        3         1       25.00   100  1      1        0                    
f_mask16 4        3         1       25.00   100  1      1        0                    
f_mask17 4        3         1       25.00   100  1      1        0                    
f_mask18 4        3         1       25.00   100  1      1        0                    
f_mask19 4        3         1       25.00   100  1      1        0                    
f_mask20 4        3         1       25.00   100  1      1        0                    
f_mask21 4        3         1       25.00   100  1      1        0                    
f_mask22 4        3         1       25.00   100  1      1        0                    
f_mask23 4        3         1       25.00   100  1      1        0                    
f_mask24 4        3         1       25.00   100  1      1        0                    
f_mask25 4        3         1       25.00   100  1      1        0                    
f_mask26 4        3         1       25.00   100  1      1        0                    
f_mask27 4        3         1       25.00   100  1      1        0                    
f_mask28 4        3         1       25.00   100  1      1        0                    
f_mask29 4        3         1       25.00   100  1      1        0                    
f_mask30 4        3         1       25.00   100  1      1        0                    
f_mask31 4        3         1       25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : INT_SRCB_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_INT_SRCB::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   INT_SRCB_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 128      96        32      25.00   


Variables for Group Instance  INT_SRCB_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
f_mask0  4        3         1       25.00   100  4      1        0                    
f_mask1  4        3         1       25.00   100  4      1        0                    
f_mask2  4        3         1       25.00   100  4      1        0                    
f_mask3  4        3         1       25.00   100  4      1        0                    
f_mask4  4        3         1       25.00   100  4      1        0                    
f_mask5  4        3         1       25.00   100  4      1        0                    
f_mask6  4        3         1       25.00   100  4      1        0                    
f_mask7  4        3         1       25.00   100  4      1        0                    
f_mask8  4        3         1       25.00   100  4      1        0                    
f_mask9  4        3         1       25.00   100  4      1        0                    
f_mask10 4        3         1       25.00   100  4      1        0                    
f_mask11 4        3         1       25.00   100  4      1        0                    
f_mask12 4        3         1       25.00   100  4      1        0                    
f_mask13 4        3         1       25.00   100  4      1        0                    
f_mask14 4        3         1       25.00   100  4      1        0                    
f_mask15 4        3         1       25.00   100  4      1        0                    
f_mask16 4        3         1       25.00   100  4      1        0                    
f_mask17 4        3         1       25.00   100  4      1        0                    
f_mask18 4        3         1       25.00   100  4      1        0                    
f_mask19 4        3         1       25.00   100  4      1        0                    
f_mask20 4        3         1       25.00   100  4      1        0                    
f_mask21 4        3         1       25.00   100  4      1        0                    
f_mask22 4        3         1       25.00   100  4      1        0                    
f_mask23 4        3         1       25.00   100  4      1        0                    
f_mask24 4        3         1       25.00   100  4      1        0                    
f_mask25 4        3         1       25.00   100  4      1        0                    
f_mask26 4        3         1       25.00   100  4      1        0                    
f_mask27 4        3         1       25.00   100  4      1        0                    
f_mask28 4        3         1       25.00   100  4      1        0                    
f_mask29 4        3         1       25.00   100  4      1        0                    
f_mask30 4        3         1       25.00   100  4      1        0                    
f_mask31 4        3         1       25.00   100  4      1        0                    


-------------------------------------------------------------------------------

Summary for Variable f_mask0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask0


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask1


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask2


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask2


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask3


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask3


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask4


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask4


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask5


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask5


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask6


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask6


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask7


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask7


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask8


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask8


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask9


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask9


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask10


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask10


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask11


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask11


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask12


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask12


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask13


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask13


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask14


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask14


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask15


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask15


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask16


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask16


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask17


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask17


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask18


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask18


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask19


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask19


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask20


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask20


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask21


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask21


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask22


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask22


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask23


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask23


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask24


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask24


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask25


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask25


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask26


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask26


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask27


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask27


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask28


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask28


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask29


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask29


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask30


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask30


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


-------------------------------------------------------------------------------

Summary for Variable f_mask31


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for f_mask31


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 34    1        


Group : test::ral_reg_CHN_SZ::cg_bits

===============================================================================
Group : test::ral_reg_CHN_SZ::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME         
 25.00 1      100    1        64           64            ch30_sz_bits 
 25.00 1      100    1        64           64            ch29_sz_bits 
 25.00 1      100    1        64           64            ch28_sz_bits 
 25.00 1      100    1        64           64            ch27_sz_bits 
 25.00 1      100    1        64           64            ch26_sz_bits 
 25.00 1      100    1        64           64            ch25_sz_bits 
 25.00 1      100    1        64           64            ch24_sz_bits 
 25.00 1      100    1        64           64            ch23_sz_bits 
 25.00 1      100    1        64           64            ch22_sz_bits 
 25.00 1      100    1        64           64            ch21_sz_bits 
 25.00 1      100    1        64           64            ch20_sz_bits 
 25.00 1      100    1        64           64            ch19_sz_bits 
 25.00 1      100    1        64           64            ch18_sz_bits 
 25.00 1      100    1        64           64            ch17_sz_bits 
 25.00 1      100    1        64           64            ch16_sz_bits 
 25.00 1      100    1        64           64            ch15_sz_bits 
 25.00 1      100    1        64           64            ch14_sz_bits 
 25.00 1      100    1        64           64            ch13_sz_bits 
 25.00 1      100    1        64           64            ch12_sz_bits 
 25.00 1      100    1        64           64            ch11_sz_bits 
 25.00 1      100    1        64           64            ch10_sz_bits 
 25.00 1      100    1        64           64            ch9_sz_bits  
 25.00 1      100    1        64           64            ch8_sz_bits  
 25.00 1      100    1        64           64            ch7_sz_bits  
 25.00 1      100    1        64           64            ch6_sz_bits  
 25.00 1      100    1        64           64            ch5_sz_bits  
 25.00 1      100    1        64           64            ch4_sz_bits  
 25.00 1      100    1        64           64            ch3_sz_bits  
 25.00 1      100    1        64           64            ch2_sz_bits  
 25.00 1      100    1        64           64            ch1_sz_bits  
 25.00 1      100    1        64           64            ch0_sz_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_SZ::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group  test::ral_reg_CHN_SZ::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  1      1        0                    
TOT_SZ   48       36        12      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch30_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch29_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch28_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch27_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch26_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch25_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch24_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch23_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch22_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch21_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch20_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch19_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch18_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch17_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch16_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch15_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch14_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch13_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch12_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch11_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch10_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch9_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch8_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch7_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch6_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch5_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch4_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch3_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch2_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch1_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_sz_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SZ::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_sz_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 96       72        24      25.00   


Variables for Group Instance  ch0_sz_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CHK_SZ   48       36        12      25.00   100  48     1        0                    
TOT_SZ   48       36        12      25.00   100  48     1        0                    


-------------------------------------------------------------------------------

Summary for Variable CHK_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for CHK_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------

Summary for Variable TOT_SZ


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 48       36        12      25.00   


User Defined Bins for TOT_SZ


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::ral_reg_CHN_A0::cg_bits

===============================================================================
Group : test::ral_reg_CHN_A0::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME         
 25.00 1      100    1        64           64            ch30_a0_bits 
 25.00 1      100    1        64           64            ch29_a0_bits 
 25.00 1      100    1        64           64            ch28_a0_bits 
 25.00 1      100    1        64           64            ch27_a0_bits 
 25.00 1      100    1        64           64            ch26_a0_bits 
 25.00 1      100    1        64           64            ch25_a0_bits 
 25.00 1      100    1        64           64            ch24_a0_bits 
 25.00 1      100    1        64           64            ch23_a0_bits 
 25.00 1      100    1        64           64            ch22_a0_bits 
 25.00 1      100    1        64           64            ch21_a0_bits 
 25.00 1      100    1        64           64            ch20_a0_bits 
 25.00 1      100    1        64           64            ch19_a0_bits 
 25.00 1      100    1        64           64            ch18_a0_bits 
 25.00 1      100    1        64           64            ch17_a0_bits 
 25.00 1      100    1        64           64            ch16_a0_bits 
 25.00 1      100    1        64           64            ch15_a0_bits 
 25.00 1      100    1        64           64            ch14_a0_bits 
 25.00 1      100    1        64           64            ch13_a0_bits 
 25.00 1      100    1        64           64            ch12_a0_bits 
 25.00 1      100    1        64           64            ch11_a0_bits 
 25.00 1      100    1        64           64            ch10_a0_bits 
 25.00 1      100    1        64           64            ch9_a0_bits  
 25.00 1      100    1        64           64            ch8_a0_bits  
 25.00 1      100    1        64           64            ch7_a0_bits  
 25.00 1      100    1        64           64            ch6_a0_bits  
 25.00 1      100    1        64           64            ch5_a0_bits  
 25.00 1      100    1        64           64            ch4_a0_bits  
 25.00 1      100    1        64           64            ch3_a0_bits  
 25.00 1      100    1        64           64            ch2_a0_bits  
 25.00 1      100    1        64           64            ch1_a0_bits  
 25.00 1      100    1        64           64            ch0_a0_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_A0::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group  test::ral_reg_CHN_A0::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 1023  1        
bit_27_rd_as_0 1023  1        
bit_26_rd_as_0 1023  1        
bit_25_rd_as_0 1023  1        
bit_24_rd_as_0 1023  1        
bit_23_rd_as_0 1023  1        
bit_22_rd_as_0 1023  1        
bit_21_rd_as_0 1023  1        
bit_20_rd_as_0 1023  1        
bit_19_rd_as_0 1023  1        
bit_18_rd_as_0 1023  1        
bit_17_rd_as_0 1023  1        
bit_16_rd_as_0 1023  1        
bit_15_rd_as_0 1023  1        
bit_14_rd_as_0 1023  1        
bit_13_rd_as_0 1023  1        
bit_12_rd_as_0 1023  1        
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch30_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch29_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch28_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch27_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch26_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch25_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch24_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch23_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch22_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch21_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch20_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch19_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch18_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch17_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch16_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch15_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch14_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch13_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch12_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch11_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch10_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch9_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch8_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch7_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch6_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch5_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch4_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch3_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch2_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch1_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_a0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_a0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch0_a0_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::ral_reg_CHN_AM0::cg_bits

===============================================================================
Group : test::ral_reg_CHN_AM0::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME          
 25.00 1      100    1        64           64            ch30_am0_bits 
 25.00 1      100    1        64           64            ch29_am0_bits 
 25.00 1      100    1        64           64            ch28_am0_bits 
 25.00 1      100    1        64           64            ch27_am0_bits 
 25.00 1      100    1        64           64            ch26_am0_bits 
 25.00 1      100    1        64           64            ch25_am0_bits 
 25.00 1      100    1        64           64            ch24_am0_bits 
 25.00 1      100    1        64           64            ch23_am0_bits 
 25.00 1      100    1        64           64            ch22_am0_bits 
 25.00 1      100    1        64           64            ch21_am0_bits 
 25.00 1      100    1        64           64            ch20_am0_bits 
 25.00 1      100    1        64           64            ch19_am0_bits 
 25.00 1      100    1        64           64            ch18_am0_bits 
 25.00 1      100    1        64           64            ch17_am0_bits 
 25.00 1      100    1        64           64            ch16_am0_bits 
 25.00 1      100    1        64           64            ch15_am0_bits 
 25.00 1      100    1        64           64            ch14_am0_bits 
 25.00 1      100    1        64           64            ch13_am0_bits 
 25.00 1      100    1        64           64            ch12_am0_bits 
 25.00 1      100    1        64           64            ch11_am0_bits 
 25.00 1      100    1        64           64            ch10_am0_bits 
 25.00 1      100    1        64           64            ch9_am0_bits  
 25.00 1      100    1        64           64            ch8_am0_bits  
 25.00 1      100    1        64           64            ch7_am0_bits  
 25.00 1      100    1        64           64            ch6_am0_bits  
 25.00 1      100    1        64           64            ch5_am0_bits  
 25.00 1      100    1        64           64            ch4_am0_bits  
 25.00 1      100    1        64           64            ch3_am0_bits  
 25.00 1      100    1        64           64            ch2_am0_bits  
 25.00 1      100    1        64           64            ch1_am0_bits  
 25.00 1      100    1        64           64            ch0_am0_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_AM0::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group  test::ral_reg_CHN_AM0::cg_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 1023  1        
bit_26_rd_as_0 1023  1        
bit_25_rd_as_0 1023  1        
bit_24_rd_as_0 1023  1        
bit_23_rd_as_0 1023  1        
bit_22_rd_as_0 1023  1        
bit_21_rd_as_0 1023  1        
bit_20_rd_as_0 1023  1        
bit_19_rd_as_0 1023  1        
bit_18_rd_as_0 1023  1        
bit_17_rd_as_0 1023  1        
bit_16_rd_as_0 1023  1        
bit_15_rd_as_0 1023  1        
bit_14_rd_as_0 1023  1        
bit_13_rd_as_0 1023  1        
bit_12_rd_as_0 1023  1        
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch30_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch29_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch28_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch27_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch26_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch25_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch24_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch23_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch22_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch21_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch20_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch19_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch18_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch17_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch16_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch15_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch14_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch13_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch12_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch11_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch10_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch9_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch8_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch7_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch6_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch5_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch4_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch3_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch2_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch1_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_am0_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM0::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_am0_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch0_am0_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::ral_reg_CHN_A1::cg_bits

===============================================================================
Group : test::ral_reg_CHN_A1::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME         
 25.00 1      100    1        64           64            ch30_a1_bits 
 25.00 1      100    1        64           64            ch29_a1_bits 
 25.00 1      100    1        64           64            ch28_a1_bits 
 25.00 1      100    1        64           64            ch27_a1_bits 
 25.00 1      100    1        64           64            ch26_a1_bits 
 25.00 1      100    1        64           64            ch25_a1_bits 
 25.00 1      100    1        64           64            ch24_a1_bits 
 25.00 1      100    1        64           64            ch23_a1_bits 
 25.00 1      100    1        64           64            ch22_a1_bits 
 25.00 1      100    1        64           64            ch21_a1_bits 
 25.00 1      100    1        64           64            ch20_a1_bits 
 25.00 1      100    1        64           64            ch19_a1_bits 
 25.00 1      100    1        64           64            ch18_a1_bits 
 25.00 1      100    1        64           64            ch17_a1_bits 
 25.00 1      100    1        64           64            ch16_a1_bits 
 25.00 1      100    1        64           64            ch15_a1_bits 
 25.00 1      100    1        64           64            ch14_a1_bits 
 25.00 1      100    1        64           64            ch13_a1_bits 
 25.00 1      100    1        64           64            ch12_a1_bits 
 25.00 1      100    1        64           64            ch11_a1_bits 
 25.00 1      100    1        64           64            ch10_a1_bits 
 25.00 1      100    1        64           64            ch9_a1_bits  
 25.00 1      100    1        64           64            ch8_a1_bits  
 25.00 1      100    1        64           64            ch7_a1_bits  
 25.00 1      100    1        64           64            ch6_a1_bits  
 25.00 1      100    1        64           64            ch5_a1_bits  
 25.00 1      100    1        64           64            ch4_a1_bits  
 25.00 1      100    1        64           64            ch3_a1_bits  
 25.00 1      100    1        64           64            ch2_a1_bits  
 25.00 1      100    1        64           64            ch1_a1_bits  
 25.00 1      100    1        64           64            ch0_a1_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_A1::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group  test::ral_reg_CHN_A1::cg_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 1054  1        
bit_27_rd_as_0 1054  1        
bit_26_rd_as_0 1054  1        
bit_25_rd_as_0 1054  1        
bit_24_rd_as_0 1054  1        
bit_23_rd_as_0 1054  1        
bit_22_rd_as_0 1054  1        
bit_21_rd_as_0 1054  1        
bit_20_rd_as_0 1054  1        
bit_19_rd_as_0 1054  1        
bit_18_rd_as_0 1054  1        
bit_17_rd_as_0 1054  1        
bit_16_rd_as_0 1054  1        
bit_15_rd_as_0 1054  1        
bit_14_rd_as_0 1054  1        
bit_13_rd_as_0 1054  1        
bit_12_rd_as_0 1054  1        
bit_11_rd_as_0 1054  1        
bit_10_rd_as_0 1054  1        
bit_9_rd_as_0  1054  1        
bit_8_rd_as_0  1054  1        
bit_7_rd_as_0  1054  1        
bit_6_rd_as_0  1054  1        
bit_5_rd_as_0  1054  1        
bit_4_rd_as_0  1054  1        
bit_3_rd_as_0  1054  1        
bit_2_rd_as_0  1054  1        
bit_1_rd_as_0  1054  1        
bit_0_rd_as_0  1054  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch30_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch29_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch28_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch27_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch26_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch25_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch24_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch23_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch22_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch21_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch20_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch19_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch18_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch17_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch16_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch15_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch14_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch13_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch12_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch11_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch10_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch9_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch8_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch7_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch6_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch5_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch4_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch3_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch2_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch1_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_a1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                          
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_A1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_a1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 116      87        29      25.00   


Variables for Group Instance  ch0_a1_bits


VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS  116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for ADDRESS


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 34    1        
bit_27_rd_as_0 34    1        
bit_26_rd_as_0 34    1        
bit_25_rd_as_0 34    1        
bit_24_rd_as_0 34    1        
bit_23_rd_as_0 34    1        
bit_22_rd_as_0 34    1        
bit_21_rd_as_0 34    1        
bit_20_rd_as_0 34    1        
bit_19_rd_as_0 34    1        
bit_18_rd_as_0 34    1        
bit_17_rd_as_0 34    1        
bit_16_rd_as_0 34    1        
bit_15_rd_as_0 34    1        
bit_14_rd_as_0 34    1        
bit_13_rd_as_0 34    1        
bit_12_rd_as_0 34    1        
bit_11_rd_as_0 34    1        
bit_10_rd_as_0 34    1        
bit_9_rd_as_0  34    1        
bit_8_rd_as_0  34    1        
bit_7_rd_as_0  34    1        
bit_6_rd_as_0  34    1        
bit_5_rd_as_0  34    1        
bit_4_rd_as_0  34    1        
bit_3_rd_as_0  34    1        
bit_2_rd_as_0  34    1        
bit_1_rd_as_0  34    1        
bit_0_rd_as_0  34    1        


Group : test::ral_reg_CHN_AM1::cg_bits

===============================================================================
Group : test::ral_reg_CHN_AM1::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME          
 25.00 1      100    1        64           64            ch30_am1_bits 
 25.00 1      100    1        64           64            ch29_am1_bits 
 25.00 1      100    1        64           64            ch28_am1_bits 
 25.00 1      100    1        64           64            ch27_am1_bits 
 25.00 1      100    1        64           64            ch26_am1_bits 
 25.00 1      100    1        64           64            ch25_am1_bits 
 25.00 1      100    1        64           64            ch24_am1_bits 
 25.00 1      100    1        64           64            ch23_am1_bits 
 25.00 1      100    1        64           64            ch22_am1_bits 
 25.00 1      100    1        64           64            ch21_am1_bits 
 25.00 1      100    1        64           64            ch20_am1_bits 
 25.00 1      100    1        64           64            ch19_am1_bits 
 25.00 1      100    1        64           64            ch18_am1_bits 
 25.00 1      100    1        64           64            ch17_am1_bits 
 25.00 1      100    1        64           64            ch16_am1_bits 
 25.00 1      100    1        64           64            ch15_am1_bits 
 25.00 1      100    1        64           64            ch14_am1_bits 
 25.00 1      100    1        64           64            ch13_am1_bits 
 25.00 1      100    1        64           64            ch12_am1_bits 
 25.00 1      100    1        64           64            ch11_am1_bits 
 25.00 1      100    1        64           64            ch10_am1_bits 
 25.00 1      100    1        64           64            ch9_am1_bits  
 25.00 1      100    1        64           64            ch8_am1_bits  
 25.00 1      100    1        64           64            ch7_am1_bits  
 25.00 1      100    1        64           64            ch6_am1_bits  
 25.00 1      100    1        64           64            ch5_am1_bits  
 25.00 1      100    1        64           64            ch4_am1_bits  
 25.00 1      100    1        64           64            ch3_am1_bits  
 25.00 1      100    1        64           64            ch2_am1_bits  
 25.00 1      100    1        64           64            ch1_am1_bits  
 25.00 1      100    1        64           64            ch0_am1_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_AM1::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group  test::ral_reg_CHN_AM1::cg_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 1023  1        
bit_26_rd_as_0 1023  1        
bit_25_rd_as_0 1023  1        
bit_24_rd_as_0 1023  1        
bit_23_rd_as_0 1023  1        
bit_22_rd_as_0 1023  1        
bit_21_rd_as_0 1023  1        
bit_20_rd_as_0 1023  1        
bit_19_rd_as_0 1023  1        
bit_18_rd_as_0 1023  1        
bit_17_rd_as_0 1023  1        
bit_16_rd_as_0 1023  1        
bit_15_rd_as_0 1023  1        
bit_14_rd_as_0 1023  1        
bit_13_rd_as_0 1023  1        
bit_12_rd_as_0 1023  1        
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch30_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch29_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch28_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch27_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch26_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch25_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch24_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch23_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch22_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch21_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch20_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch19_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch18_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch17_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch16_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch15_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch14_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch13_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch12_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch11_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch10_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch9_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch8_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch7_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch6_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch5_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch4_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch3_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch2_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch1_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_am1_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                           
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_AM1::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_am1_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch0_am1_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::ral_reg_CHN_DESC::cg_bits

===============================================================================
Group : test::ral_reg_CHN_DESC::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME           
 25.00 1      100    1        64           64            ch30_desc_bits 
 25.00 1      100    1        64           64            ch29_desc_bits 
 25.00 1      100    1        64           64            ch28_desc_bits 
 25.00 1      100    1        64           64            ch27_desc_bits 
 25.00 1      100    1        64           64            ch26_desc_bits 
 25.00 1      100    1        64           64            ch25_desc_bits 
 25.00 1      100    1        64           64            ch24_desc_bits 
 25.00 1      100    1        64           64            ch23_desc_bits 
 25.00 1      100    1        64           64            ch22_desc_bits 
 25.00 1      100    1        64           64            ch21_desc_bits 
 25.00 1      100    1        64           64            ch20_desc_bits 
 25.00 1      100    1        64           64            ch19_desc_bits 
 25.00 1      100    1        64           64            ch18_desc_bits 
 25.00 1      100    1        64           64            ch17_desc_bits 
 25.00 1      100    1        64           64            ch16_desc_bits 
 25.00 1      100    1        64           64            ch15_desc_bits 
 25.00 1      100    1        64           64            ch14_desc_bits 
 25.00 1      100    1        64           64            ch13_desc_bits 
 25.00 1      100    1        64           64            ch12_desc_bits 
 25.00 1      100    1        64           64            ch11_desc_bits 
 25.00 1      100    1        64           64            ch10_desc_bits 
 25.00 1      100    1        64           64            ch9_desc_bits  
 25.00 1      100    1        64           64            ch8_desc_bits  
 25.00 1      100    1        64           64            ch7_desc_bits  
 25.00 1      100    1        64           64            ch6_desc_bits  
 25.00 1      100    1        64           64            ch5_desc_bits  
 25.00 1      100    1        64           64            ch4_desc_bits  
 25.00 1      100    1        64           64            ch3_desc_bits  
 25.00 1      100    1        64           64            ch2_desc_bits  
 25.00 1      100    1        64           64            ch1_desc_bits  
 25.00 1      100    1        64           64            ch0_desc_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_DESC::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group  test::ral_reg_CHN_DESC::cg_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 1023  1        
bit_26_rd_as_0 1023  1        
bit_25_rd_as_0 1023  1        
bit_24_rd_as_0 1023  1        
bit_23_rd_as_0 1023  1        
bit_22_rd_as_0 1023  1        
bit_21_rd_as_0 1023  1        
bit_20_rd_as_0 1023  1        
bit_19_rd_as_0 1023  1        
bit_18_rd_as_0 1023  1        
bit_17_rd_as_0 1023  1        
bit_16_rd_as_0 1023  1        
bit_15_rd_as_0 1023  1        
bit_14_rd_as_0 1023  1        
bit_13_rd_as_0 1023  1        
bit_12_rd_as_0 1023  1        
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch30_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch29_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch28_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch27_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch26_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch25_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch24_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch23_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch22_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch21_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch20_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch19_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch18_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch17_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch16_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch15_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch14_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch13_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch12_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch11_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch10_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch9_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch8_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch7_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch6_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch5_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch4_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch3_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch2_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch1_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_desc_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_DESC::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_desc_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 112      84        28      25.00   


Variables for Group Instance  ch0_desc_bits


VARIABLE     EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
ADDRESS_MASK 112      84        28      25.00   100  112    1        0                    


-------------------------------------------------------------------------------

Summary for Variable ADDRESS_MASK


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 112      84        28      25.00   


User Defined Bins for ADDRESS_MASK


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::ral_reg_CHN_SWPTR::cg_bits

===============================================================================
Group : test::ral_reg_CHN_SWPTR::cg_bits
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
 25.00  25.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

31 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME            
 25.00 1      100    1        64           64            ch30_swptr_bits 
 25.00 1      100    1        64           64            ch29_swptr_bits 
 25.00 1      100    1        64           64            ch28_swptr_bits 
 25.00 1      100    1        64           64            ch27_swptr_bits 
 25.00 1      100    1        64           64            ch26_swptr_bits 
 25.00 1      100    1        64           64            ch25_swptr_bits 
 25.00 1      100    1        64           64            ch24_swptr_bits 
 25.00 1      100    1        64           64            ch23_swptr_bits 
 25.00 1      100    1        64           64            ch22_swptr_bits 
 25.00 1      100    1        64           64            ch21_swptr_bits 
 25.00 1      100    1        64           64            ch20_swptr_bits 
 25.00 1      100    1        64           64            ch19_swptr_bits 
 25.00 1      100    1        64           64            ch18_swptr_bits 
 25.00 1      100    1        64           64            ch17_swptr_bits 
 25.00 1      100    1        64           64            ch16_swptr_bits 
 25.00 1      100    1        64           64            ch15_swptr_bits 
 25.00 1      100    1        64           64            ch14_swptr_bits 
 25.00 1      100    1        64           64            ch13_swptr_bits 
 25.00 1      100    1        64           64            ch12_swptr_bits 
 25.00 1      100    1        64           64            ch11_swptr_bits 
 25.00 1      100    1        64           64            ch10_swptr_bits 
 25.00 1      100    1        64           64            ch9_swptr_bits  
 25.00 1      100    1        64           64            ch8_swptr_bits  
 25.00 1      100    1        64           64            ch7_swptr_bits  
 25.00 1      100    1        64           64            ch6_swptr_bits  
 25.00 1      100    1        64           64            ch5_swptr_bits  
 25.00 1      100    1        64           64            ch4_swptr_bits  
 25.00 1      100    1        64           64            ch3_swptr_bits  
 25.00 1      100    1        64           64            ch2_swptr_bits  
 25.00 1      100    1        64           64            ch1_swptr_bits  
 25.00 1      100    1        64           64            ch0_swptr_bits  




-------------------------------------------------------------------------------

Summary for Group   test::ral_reg_CHN_SWPTR::cg_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group  test::ral_reg_CHN_SWPTR::cg_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  1      1        0                    
SW_POINTER 116      87        29      25.00   100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 1023  1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 1023  1        
bit_27_rd_as_0 1023  1        
bit_26_rd_as_0 1023  1        
bit_25_rd_as_0 1023  1        
bit_24_rd_as_0 1023  1        
bit_23_rd_as_0 1023  1        
bit_22_rd_as_0 1023  1        
bit_21_rd_as_0 1023  1        
bit_20_rd_as_0 1023  1        
bit_19_rd_as_0 1023  1        
bit_18_rd_as_0 1023  1        
bit_17_rd_as_0 1023  1        
bit_16_rd_as_0 1023  1        
bit_15_rd_as_0 1023  1        
bit_14_rd_as_0 1023  1        
bit_13_rd_as_0 1023  1        
bit_12_rd_as_0 1023  1        
bit_11_rd_as_0 1023  1        
bit_10_rd_as_0 1023  1        
bit_9_rd_as_0  1023  1        
bit_8_rd_as_0  1023  1        
bit_7_rd_as_0  1023  1        
bit_6_rd_as_0  1023  1        
bit_5_rd_as_0  1023  1        
bit_4_rd_as_0  1023  1        
bit_3_rd_as_0  1023  1        
bit_2_rd_as_0  1023  1        
bit_1_rd_as_0  1023  1        
bit_0_rd_as_0  1023  1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch30_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch30_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch30_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch29_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch29_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch29_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch28_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch28_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch28_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch27_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch27_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch27_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch26_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch26_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch26_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch25_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch25_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch25_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch24_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch24_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch24_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch23_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch23_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch23_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch22_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch22_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch22_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch21_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch21_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch21_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch20_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch20_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch20_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch19_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch19_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch19_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch18_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch18_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch18_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch17_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch17_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch17_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch16_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch16_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch16_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch15_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch15_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch15_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch14_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch14_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch14_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch13_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch13_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch13_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch12_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch12_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch12_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch11_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch11_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch11_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch10_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch10_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch10_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch9_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch9_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch9_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch8_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch8_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch8_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch7_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch7_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch7_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch6_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch6_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch6_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch5_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch5_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch5_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch4_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch4_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch4_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch3_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch3_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch3_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch2_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch2_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch2_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch1_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch1_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch1_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : ch0_swptr_bits
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 25.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                             
 25.00  25.00    1      100    1        1            64           64                    test::ral_reg_CHN_SWPTR::cg_bits 



-------------------------------------------------------------------------------

Summary for Group Instance   ch0_swptr_bits



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 120      90        30      25.00   


Variables for Group Instance  ch0_swptr_bits


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
SWPTR_EN   4        3         1       25.00   100  4      1        0                    
SW_POINTER 116      87        29      25.00   100  116    1        0                    


-------------------------------------------------------------------------------

Summary for Variable SWPTR_EN


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 4        3         1       25.00   


User Defined Bins for SWPTR_EN


Uncovered bins

NAME          COUNT AT LEAST NUMBER 
bit_0_rd_as_1 0     1        1      
bit_0_wr_as_1 0     1        1      
bit_0_wr_as_0 0     1        1      


Covered bins

NAME          COUNT AT LEAST 
bit_0_rd_as_0 33    1        


-------------------------------------------------------------------------------

Summary for Variable SW_POINTER


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 116      87        29      25.00   


User Defined Bins for SW_POINTER


Uncovered bins

NAME           COUNT AT LEAST NUMBER 
bit_28_rd_as_1 0     1        1      
bit_28_wr_as_1 0     1        1      
bit_28_wr_as_0 0     1        1      
bit_27_rd_as_1 0     1        1      
bit_27_wr_as_1 0     1        1      
bit_27_wr_as_0 0     1        1      
bit_26_rd_as_1 0     1        1      
bit_26_wr_as_1 0     1        1      
bit_26_wr_as_0 0     1        1      
bit_25_rd_as_1 0     1        1      
bit_25_wr_as_1 0     1        1      
bit_25_wr_as_0 0     1        1      
bit_24_rd_as_1 0     1        1      
bit_24_wr_as_1 0     1        1      
bit_24_wr_as_0 0     1        1      
bit_23_rd_as_1 0     1        1      
bit_23_wr_as_1 0     1        1      
bit_23_wr_as_0 0     1        1      
bit_22_rd_as_1 0     1        1      
bit_22_wr_as_1 0     1        1      
bit_22_wr_as_0 0     1        1      
bit_21_rd_as_1 0     1        1      
bit_21_wr_as_1 0     1        1      
bit_21_wr_as_0 0     1        1      
bit_20_rd_as_1 0     1        1      
bit_20_wr_as_1 0     1        1      
bit_20_wr_as_0 0     1        1      
bit_19_rd_as_1 0     1        1      
bit_19_wr_as_1 0     1        1      
bit_19_wr_as_0 0     1        1      
bit_18_rd_as_1 0     1        1      
bit_18_wr_as_1 0     1        1      
bit_18_wr_as_0 0     1        1      
bit_17_rd_as_1 0     1        1      
bit_17_wr_as_1 0     1        1      
bit_17_wr_as_0 0     1        1      
bit_16_rd_as_1 0     1        1      
bit_16_wr_as_1 0     1        1      
bit_16_wr_as_0 0     1        1      
bit_15_rd_as_1 0     1        1      
bit_15_wr_as_1 0     1        1      
bit_15_wr_as_0 0     1        1      
bit_14_rd_as_1 0     1        1      
bit_14_wr_as_1 0     1        1      
bit_14_wr_as_0 0     1        1      
bit_13_rd_as_1 0     1        1      
bit_13_wr_as_1 0     1        1      
bit_13_wr_as_0 0     1        1      
bit_12_rd_as_1 0     1        1      
bit_12_wr_as_1 0     1        1      
bit_12_wr_as_0 0     1        1      
bit_11_rd_as_1 0     1        1      
bit_11_wr_as_1 0     1        1      
bit_11_wr_as_0 0     1        1      
bit_10_rd_as_1 0     1        1      
bit_10_wr_as_1 0     1        1      
bit_10_wr_as_0 0     1        1      
bit_9_rd_as_1  0     1        1      
bit_9_wr_as_1  0     1        1      
bit_9_wr_as_0  0     1        1      
bit_8_rd_as_1  0     1        1      
bit_8_wr_as_1  0     1        1      
bit_8_wr_as_0  0     1        1      
bit_7_rd_as_1  0     1        1      
bit_7_wr_as_1  0     1        1      
bit_7_wr_as_0  0     1        1      
bit_6_rd_as_1  0     1        1      
bit_6_wr_as_1  0     1        1      
bit_6_wr_as_0  0     1        1      
bit_5_rd_as_1  0     1        1      
bit_5_wr_as_1  0     1        1      
bit_5_wr_as_0  0     1        1      
bit_4_rd_as_1  0     1        1      
bit_4_wr_as_1  0     1        1      
bit_4_wr_as_0  0     1        1      
bit_3_rd_as_1  0     1        1      
bit_3_wr_as_1  0     1        1      
bit_3_wr_as_0  0     1        1      
bit_2_rd_as_1  0     1        1      
bit_2_wr_as_1  0     1        1      
bit_2_wr_as_0  0     1        1      
bit_1_rd_as_1  0     1        1      
bit_1_wr_as_1  0     1        1      
bit_1_wr_as_0  0     1        1      
bit_0_rd_as_1  0     1        1      
bit_0_wr_as_1  0     1        1      
bit_0_wr_as_0  0     1        1      


Covered bins

NAME           COUNT AT LEAST 
bit_28_rd_as_0 33    1        
bit_27_rd_as_0 33    1        
bit_26_rd_as_0 33    1        
bit_25_rd_as_0 33    1        
bit_24_rd_as_0 33    1        
bit_23_rd_as_0 33    1        
bit_22_rd_as_0 33    1        
bit_21_rd_as_0 33    1        
bit_20_rd_as_0 33    1        
bit_19_rd_as_0 33    1        
bit_18_rd_as_0 33    1        
bit_17_rd_as_0 33    1        
bit_16_rd_as_0 33    1        
bit_15_rd_as_0 33    1        
bit_14_rd_as_0 33    1        
bit_13_rd_as_0 33    1        
bit_12_rd_as_0 33    1        
bit_11_rd_as_0 33    1        
bit_10_rd_as_0 33    1        
bit_9_rd_as_0  33    1        
bit_8_rd_as_0  33    1        
bit_7_rd_as_0  33    1        
bit_6_rd_as_0  33    1        
bit_5_rd_as_0  33    1        
bit_4_rd_as_0  33    1        
bit_3_rd_as_0  33    1        
bit_2_rd_as_0  33    1        
bit_1_rd_as_0  33    1        
bit_0_rd_as_0  33    1        


Group : test::wb_dma_env_cov::cg_trans

===============================================================================
Group : test::wb_dma_env_cov::cg_trans
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
 73.33 1      100    1        64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/src/wb_dma_env_cov.sv



-------------------------------------------------------------------------------

Summary for Group   test::wb_dma_env_cov::cg_trans



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 9        4         5       73.33   


Variables for Group  test::wb_dma_env_cov::cg_trans


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
tr.kind    5        4         1       20.00   100  1      1        0                    
tr.address 3        0         3       100.00  100  1      1        0                    
tga        1        0         1       100.00  100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable tr.kind


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 5        4         1       20.00   


User Defined Bins for tr.kind


Uncovered bins

NAME        COUNT AT LEAST NUMBER 
auto_READ   0     1        1      
auto_BLK_RD 0     1        1      
auto_BLK_WR 0     1        1      
auto_RMW    0     1        1      


Covered bins

NAME       COUNT AT LEAST 
auto_WRITE 17024 1        


-------------------------------------------------------------------------------

Summary for Variable tr.address


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 3        0         3       100.00  


User Defined Bins for tr.address


Bins

NAME COUNT AT LEAST 
hi   14530 1        
med  831   1        
lo   865   1        


-------------------------------------------------------------------------------

Summary for Variable tga


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for tga


Excluded/Illegal bins

NAME COUNT STATUS   
hi   0     Excluded 


Covered bins

NAME COUNT AT LEAST 
sane 17024 1        


Group : test::ral_block_wb_dma::cg_addr

===============================================================================
Group : test::ral_block_wb_dma::cg_addr
===============================================================================
SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING 
100.00 100.00    1      100    1        1            64           64            


Source File(s) : 

/slowfs/vgcs13/srivats/clone_me/Practical_UVM_EXAMPLES/Part_5/CoverageClosure_non_UVM/sim/../bench/wb_dma_uvm/env/ral_wb_dma.sv

1 Instances:

SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING NAME   
100.00 1      100    1        64           64            wb_dma 




-------------------------------------------------------------------------------

Summary for Group   test::ral_block_wb_dma::cg_addr



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 253      0         253     100.00  


Variables for Group  test::ral_block_wb_dma::cg_addr


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CSR        1        0         1       100.00  100  1      1        0                    
INT_MASKA  1        0         1       100.00  100  1      1        0                    
INT_MASKB  1        0         1       100.00  100  1      1        0                    
INT_SRCA   1        0         1       100.00  100  1      1        0                    
INT_SRCB   1        0         1       100.00  100  1      1        0                    
CH0_CSR    1        0         1       100.00  100  1      1        0                    
ch0_sz     1        0         1       100.00  100  1      1        0                    
ch0_a0     1        0         1       100.00  100  1      1        0                    
ch0_am0    1        0         1       100.00  100  1      1        0                    
ch0_a1     1        0         1       100.00  100  1      1        0                    
ch0_am1    1        0         1       100.00  100  1      1        0                    
ch0_desc   1        0         1       100.00  100  1      1        0                    
ch0_swptr  1        0         1       100.00  100  1      1        0                    
ch1_csr    1        0         1       100.00  100  1      1        0                    
ch1_sz     1        0         1       100.00  100  1      1        0                    
ch1_a0     1        0         1       100.00  100  1      1        0                    
ch1_am0    1        0         1       100.00  100  1      1        0                    
ch1_a1     1        0         1       100.00  100  1      1        0                    
ch1_am1    1        0         1       100.00  100  1      1        0                    
ch1_desc   1        0         1       100.00  100  1      1        0                    
ch1_swptr  1        0         1       100.00  100  1      1        0                    
ch2_csr    1        0         1       100.00  100  1      1        0                    
ch2_sz     1        0         1       100.00  100  1      1        0                    
ch2_a0     1        0         1       100.00  100  1      1        0                    
ch2_am0    1        0         1       100.00  100  1      1        0                    
ch2_a1     1        0         1       100.00  100  1      1        0                    
ch2_am1    1        0         1       100.00  100  1      1        0                    
ch2_desc   1        0         1       100.00  100  1      1        0                    
ch2_swptr  1        0         1       100.00  100  1      1        0                    
ch3_csr    1        0         1       100.00  100  1      1        0                    
ch3_sz     1        0         1       100.00  100  1      1        0                    
ch3_a0     1        0         1       100.00  100  1      1        0                    
ch3_am0    1        0         1       100.00  100  1      1        0                    
ch3_a1     1        0         1       100.00  100  1      1        0                    
ch3_am1    1        0         1       100.00  100  1      1        0                    
ch3_desc   1        0         1       100.00  100  1      1        0                    
ch3_swptr  1        0         1       100.00  100  1      1        0                    
ch4_csr    1        0         1       100.00  100  1      1        0                    
ch4_sz     1        0         1       100.00  100  1      1        0                    
ch4_a0     1        0         1       100.00  100  1      1        0                    
ch4_am0    1        0         1       100.00  100  1      1        0                    
ch4_a1     1        0         1       100.00  100  1      1        0                    
ch4_am1    1        0         1       100.00  100  1      1        0                    
ch4_desc   1        0         1       100.00  100  1      1        0                    
ch4_swptr  1        0         1       100.00  100  1      1        0                    
ch5_csr    1        0         1       100.00  100  1      1        0                    
ch5_sz     1        0         1       100.00  100  1      1        0                    
ch5_a0     1        0         1       100.00  100  1      1        0                    
ch5_am0    1        0         1       100.00  100  1      1        0                    
ch5_a1     1        0         1       100.00  100  1      1        0                    
ch5_am1    1        0         1       100.00  100  1      1        0                    
ch5_desc   1        0         1       100.00  100  1      1        0                    
ch5_swptr  1        0         1       100.00  100  1      1        0                    
ch6_csr    1        0         1       100.00  100  1      1        0                    
ch6_sz     1        0         1       100.00  100  1      1        0                    
ch6_a0     1        0         1       100.00  100  1      1        0                    
ch6_am0    1        0         1       100.00  100  1      1        0                    
ch6_a1     1        0         1       100.00  100  1      1        0                    
ch6_am1    1        0         1       100.00  100  1      1        0                    
ch6_desc   1        0         1       100.00  100  1      1        0                    
ch6_swptr  1        0         1       100.00  100  1      1        0                    
ch7_csr    1        0         1       100.00  100  1      1        0                    
ch7_sz     1        0         1       100.00  100  1      1        0                    
ch7_a0     1        0         1       100.00  100  1      1        0                    
ch7_am0    1        0         1       100.00  100  1      1        0                    
ch7_a1     1        0         1       100.00  100  1      1        0                    
ch7_am1    1        0         1       100.00  100  1      1        0                    
ch7_desc   1        0         1       100.00  100  1      1        0                    
ch7_swptr  1        0         1       100.00  100  1      1        0                    
ch8_csr    1        0         1       100.00  100  1      1        0                    
ch8_sz     1        0         1       100.00  100  1      1        0                    
ch8_a0     1        0         1       100.00  100  1      1        0                    
ch8_am0    1        0         1       100.00  100  1      1        0                    
ch8_a1     1        0         1       100.00  100  1      1        0                    
ch8_am1    1        0         1       100.00  100  1      1        0                    
ch8_desc   1        0         1       100.00  100  1      1        0                    
ch8_swptr  1        0         1       100.00  100  1      1        0                    
ch9_csr    1        0         1       100.00  100  1      1        0                    
ch9_sz     1        0         1       100.00  100  1      1        0                    
ch9_a0     1        0         1       100.00  100  1      1        0                    
ch9_am0    1        0         1       100.00  100  1      1        0                    
ch9_a1     1        0         1       100.00  100  1      1        0                    
ch9_am1    1        0         1       100.00  100  1      1        0                    
ch9_desc   1        0         1       100.00  100  1      1        0                    
ch9_swptr  1        0         1       100.00  100  1      1        0                    
ch10_csr   1        0         1       100.00  100  1      1        0                    
ch10_sz    1        0         1       100.00  100  1      1        0                    
ch10_a0    1        0         1       100.00  100  1      1        0                    
ch10_am0   1        0         1       100.00  100  1      1        0                    
ch10_a1    1        0         1       100.00  100  1      1        0                    
ch10_am1   1        0         1       100.00  100  1      1        0                    
ch10_desc  1        0         1       100.00  100  1      1        0                    
ch10_swptr 1        0         1       100.00  100  1      1        0                    
ch11_csr   1        0         1       100.00  100  1      1        0                    
ch11_sz    1        0         1       100.00  100  1      1        0                    
ch11_a0    1        0         1       100.00  100  1      1        0                    
ch11_am0   1        0         1       100.00  100  1      1        0                    
ch11_a1    1        0         1       100.00  100  1      1        0                    
ch11_am1   1        0         1       100.00  100  1      1        0                    
ch11_desc  1        0         1       100.00  100  1      1        0                    
ch11_swptr 1        0         1       100.00  100  1      1        0                    
ch12_csr   1        0         1       100.00  100  1      1        0                    
ch12_sz    1        0         1       100.00  100  1      1        0                    
ch12_a0    1        0         1       100.00  100  1      1        0                    
ch12_am0   1        0         1       100.00  100  1      1        0                    
ch12_a1    1        0         1       100.00  100  1      1        0                    
ch12_am1   1        0         1       100.00  100  1      1        0                    
ch12_desc  1        0         1       100.00  100  1      1        0                    
ch12_swptr 1        0         1       100.00  100  1      1        0                    
ch13_csr   1        0         1       100.00  100  1      1        0                    
ch13_sz    1        0         1       100.00  100  1      1        0                    
ch13_a0    1        0         1       100.00  100  1      1        0                    
ch13_am0   1        0         1       100.00  100  1      1        0                    
ch13_a1    1        0         1       100.00  100  1      1        0                    
ch13_am1   1        0         1       100.00  100  1      1        0                    
ch13_desc  1        0         1       100.00  100  1      1        0                    
ch13_swptr 1        0         1       100.00  100  1      1        0                    
ch14_csr   1        0         1       100.00  100  1      1        0                    
ch14_sz    1        0         1       100.00  100  1      1        0                    
ch14_a0    1        0         1       100.00  100  1      1        0                    
ch14_am0   1        0         1       100.00  100  1      1        0                    
ch14_a1    1        0         1       100.00  100  1      1        0                    
ch14_am1   1        0         1       100.00  100  1      1        0                    
ch14_desc  1        0         1       100.00  100  1      1        0                    
ch14_swptr 1        0         1       100.00  100  1      1        0                    
ch15_csr   1        0         1       100.00  100  1      1        0                    
ch15_sz    1        0         1       100.00  100  1      1        0                    
ch15_a0    1        0         1       100.00  100  1      1        0                    
ch15_am0   1        0         1       100.00  100  1      1        0                    
ch15_a1    1        0         1       100.00  100  1      1        0                    
ch15_am1   1        0         1       100.00  100  1      1        0                    
ch15_desc  1        0         1       100.00  100  1      1        0                    
ch15_swptr 1        0         1       100.00  100  1      1        0                    
ch16_csr   1        0         1       100.00  100  1      1        0                    
ch16_sz    1        0         1       100.00  100  1      1        0                    
ch16_a0    1        0         1       100.00  100  1      1        0                    
ch16_am0   1        0         1       100.00  100  1      1        0                    
ch16_a1    1        0         1       100.00  100  1      1        0                    
ch16_am1   1        0         1       100.00  100  1      1        0                    
ch16_desc  1        0         1       100.00  100  1      1        0                    
ch16_swptr 1        0         1       100.00  100  1      1        0                    
ch17_csr   1        0         1       100.00  100  1      1        0                    
ch17_sz    1        0         1       100.00  100  1      1        0                    
ch17_a0    1        0         1       100.00  100  1      1        0                    
ch17_am0   1        0         1       100.00  100  1      1        0                    
ch17_a1    1        0         1       100.00  100  1      1        0                    
ch17_am1   1        0         1       100.00  100  1      1        0                    
ch17_desc  1        0         1       100.00  100  1      1        0                    
ch17_swptr 1        0         1       100.00  100  1      1        0                    
ch18_csr   1        0         1       100.00  100  1      1        0                    
ch18_sz    1        0         1       100.00  100  1      1        0                    
ch18_a0    1        0         1       100.00  100  1      1        0                    
ch18_am0   1        0         1       100.00  100  1      1        0                    
ch18_a1    1        0         1       100.00  100  1      1        0                    
ch18_am1   1        0         1       100.00  100  1      1        0                    
ch18_desc  1        0         1       100.00  100  1      1        0                    
ch18_swptr 1        0         1       100.00  100  1      1        0                    
ch19_csr   1        0         1       100.00  100  1      1        0                    
ch19_sz    1        0         1       100.00  100  1      1        0                    
ch19_a0    1        0         1       100.00  100  1      1        0                    
ch19_am0   1        0         1       100.00  100  1      1        0                    
ch19_a1    1        0         1       100.00  100  1      1        0                    
ch19_am1   1        0         1       100.00  100  1      1        0                    
ch19_desc  1        0         1       100.00  100  1      1        0                    
ch19_swptr 1        0         1       100.00  100  1      1        0                    
ch20_csr   1        0         1       100.00  100  1      1        0                    
ch20_sz    1        0         1       100.00  100  1      1        0                    
ch20_a0    1        0         1       100.00  100  1      1        0                    
ch20_am0   1        0         1       100.00  100  1      1        0                    
ch20_a1    1        0         1       100.00  100  1      1        0                    
ch20_am1   1        0         1       100.00  100  1      1        0                    
ch20_desc  1        0         1       100.00  100  1      1        0                    
ch20_swptr 1        0         1       100.00  100  1      1        0                    
ch21_csr   1        0         1       100.00  100  1      1        0                    
ch21_sz    1        0         1       100.00  100  1      1        0                    
ch21_a0    1        0         1       100.00  100  1      1        0                    
ch21_am0   1        0         1       100.00  100  1      1        0                    
ch21_a1    1        0         1       100.00  100  1      1        0                    
ch21_am1   1        0         1       100.00  100  1      1        0                    
ch21_desc  1        0         1       100.00  100  1      1        0                    
ch21_swptr 1        0         1       100.00  100  1      1        0                    
ch22_csr   1        0         1       100.00  100  1      1        0                    
ch22_sz    1        0         1       100.00  100  1      1        0                    
ch22_a0    1        0         1       100.00  100  1      1        0                    
ch22_am0   1        0         1       100.00  100  1      1        0                    
ch22_a1    1        0         1       100.00  100  1      1        0                    
ch22_am1   1        0         1       100.00  100  1      1        0                    
ch22_desc  1        0         1       100.00  100  1      1        0                    
ch22_swptr 1        0         1       100.00  100  1      1        0                    
ch23_csr   1        0         1       100.00  100  1      1        0                    
ch23_sz    1        0         1       100.00  100  1      1        0                    
ch23_a0    1        0         1       100.00  100  1      1        0                    
ch23_am0   1        0         1       100.00  100  1      1        0                    
ch23_a1    1        0         1       100.00  100  1      1        0                    
ch23_am1   1        0         1       100.00  100  1      1        0                    
ch23_desc  1        0         1       100.00  100  1      1        0                    
ch23_swptr 1        0         1       100.00  100  1      1        0                    
ch24_csr   1        0         1       100.00  100  1      1        0                    
ch24_sz    1        0         1       100.00  100  1      1        0                    
ch24_a0    1        0         1       100.00  100  1      1        0                    
ch24_am0   1        0         1       100.00  100  1      1        0                    
ch24_a1    1        0         1       100.00  100  1      1        0                    
ch24_am1   1        0         1       100.00  100  1      1        0                    
ch24_desc  1        0         1       100.00  100  1      1        0                    
ch24_swptr 1        0         1       100.00  100  1      1        0                    
ch25_csr   1        0         1       100.00  100  1      1        0                    
ch25_sz    1        0         1       100.00  100  1      1        0                    
ch25_a0    1        0         1       100.00  100  1      1        0                    
ch25_am0   1        0         1       100.00  100  1      1        0                    
ch25_a1    1        0         1       100.00  100  1      1        0                    
ch25_am1   1        0         1       100.00  100  1      1        0                    
ch25_desc  1        0         1       100.00  100  1      1        0                    
ch25_swptr 1        0         1       100.00  100  1      1        0                    
ch26_csr   1        0         1       100.00  100  1      1        0                    
ch26_sz    1        0         1       100.00  100  1      1        0                    
ch26_a0    1        0         1       100.00  100  1      1        0                    
ch26_am0   1        0         1       100.00  100  1      1        0                    
ch26_a1    1        0         1       100.00  100  1      1        0                    
ch26_am1   1        0         1       100.00  100  1      1        0                    
ch26_desc  1        0         1       100.00  100  1      1        0                    
ch26_swptr 1        0         1       100.00  100  1      1        0                    
ch27_csr   1        0         1       100.00  100  1      1        0                    
ch27_sz    1        0         1       100.00  100  1      1        0                    
ch27_a0    1        0         1       100.00  100  1      1        0                    
ch27_am0   1        0         1       100.00  100  1      1        0                    
ch27_a1    1        0         1       100.00  100  1      1        0                    
ch27_am1   1        0         1       100.00  100  1      1        0                    
ch27_desc  1        0         1       100.00  100  1      1        0                    
ch27_swptr 1        0         1       100.00  100  1      1        0                    
ch28_csr   1        0         1       100.00  100  1      1        0                    
ch28_sz    1        0         1       100.00  100  1      1        0                    
ch28_a0    1        0         1       100.00  100  1      1        0                    
ch28_am0   1        0         1       100.00  100  1      1        0                    
ch28_a1    1        0         1       100.00  100  1      1        0                    
ch28_am1   1        0         1       100.00  100  1      1        0                    
ch28_desc  1        0         1       100.00  100  1      1        0                    
ch28_swptr 1        0         1       100.00  100  1      1        0                    
ch29_csr   1        0         1       100.00  100  1      1        0                    
ch29_sz    1        0         1       100.00  100  1      1        0                    
ch29_a0    1        0         1       100.00  100  1      1        0                    
ch29_am0   1        0         1       100.00  100  1      1        0                    
ch29_a1    1        0         1       100.00  100  1      1        0                    
ch29_am1   1        0         1       100.00  100  1      1        0                    
ch29_desc  1        0         1       100.00  100  1      1        0                    
ch29_swptr 1        0         1       100.00  100  1      1        0                    
ch30_csr   1        0         1       100.00  100  1      1        0                    
ch30_sz    1        0         1       100.00  100  1      1        0                    
ch30_a0    1        0         1       100.00  100  1      1        0                    
ch30_am0   1        0         1       100.00  100  1      1        0                    
ch30_a1    1        0         1       100.00  100  1      1        0                    
ch30_am1   1        0         1       100.00  100  1      1        0                    
ch30_desc  1        0         1       100.00  100  1      1        0                    
ch30_swptr 1        0         1       100.00  100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable CSR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for CSR


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable INT_MASKA


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_MASKA


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_MASKB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_MASKB


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_SRCA


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_SRCA


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_SRCB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_SRCB


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable CH0_CSR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for CH0_CSR


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------
===============================================================================
Group Instance : wb_dma
===============================================================================
SCORE  WEIGHT GOAL   AT LEAST AUTO BIN MAX PRINT MISSING 
100.00 1      100    1        64           64            


Group:

SCORE  INSTANCES WEIGHT GOAL   AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME                            
100.00 100.00    1      100    1        1            64           64                    test::ral_block_wb_dma::cg_addr 



-------------------------------------------------------------------------------

Summary for Group Instance   wb_dma



CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
Variables 253      0         253     100.00  


Variables for Group Instance  wb_dma


VARIABLE   EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT 
CSR        1        0         1       100.00  100  1      1        0                    
INT_MASKA  1        0         1       100.00  100  1      1        0                    
INT_MASKB  1        0         1       100.00  100  1      1        0                    
INT_SRCA   1        0         1       100.00  100  1      1        0                    
INT_SRCB   1        0         1       100.00  100  1      1        0                    
CH0_CSR    1        0         1       100.00  100  1      1        0                    
ch0_sz     1        0         1       100.00  100  1      1        0                    
ch0_a0     1        0         1       100.00  100  1      1        0                    
ch0_am0    1        0         1       100.00  100  1      1        0                    
ch0_a1     1        0         1       100.00  100  1      1        0                    
ch0_am1    1        0         1       100.00  100  1      1        0                    
ch0_desc   1        0         1       100.00  100  1      1        0                    
ch0_swptr  1        0         1       100.00  100  1      1        0                    
ch1_csr    1        0         1       100.00  100  1      1        0                    
ch1_sz     1        0         1       100.00  100  1      1        0                    
ch1_a0     1        0         1       100.00  100  1      1        0                    
ch1_am0    1        0         1       100.00  100  1      1        0                    
ch1_a1     1        0         1       100.00  100  1      1        0                    
ch1_am1    1        0         1       100.00  100  1      1        0                    
ch1_desc   1        0         1       100.00  100  1      1        0                    
ch1_swptr  1        0         1       100.00  100  1      1        0                    
ch2_csr    1        0         1       100.00  100  1      1        0                    
ch2_sz     1        0         1       100.00  100  1      1        0                    
ch2_a0     1        0         1       100.00  100  1      1        0                    
ch2_am0    1        0         1       100.00  100  1      1        0                    
ch2_a1     1        0         1       100.00  100  1      1        0                    
ch2_am1    1        0         1       100.00  100  1      1        0                    
ch2_desc   1        0         1       100.00  100  1      1        0                    
ch2_swptr  1        0         1       100.00  100  1      1        0                    
ch3_csr    1        0         1       100.00  100  1      1        0                    
ch3_sz     1        0         1       100.00  100  1      1        0                    
ch3_a0     1        0         1       100.00  100  1      1        0                    
ch3_am0    1        0         1       100.00  100  1      1        0                    
ch3_a1     1        0         1       100.00  100  1      1        0                    
ch3_am1    1        0         1       100.00  100  1      1        0                    
ch3_desc   1        0         1       100.00  100  1      1        0                    
ch3_swptr  1        0         1       100.00  100  1      1        0                    
ch4_csr    1        0         1       100.00  100  1      1        0                    
ch4_sz     1        0         1       100.00  100  1      1        0                    
ch4_a0     1        0         1       100.00  100  1      1        0                    
ch4_am0    1        0         1       100.00  100  1      1        0                    
ch4_a1     1        0         1       100.00  100  1      1        0                    
ch4_am1    1        0         1       100.00  100  1      1        0                    
ch4_desc   1        0         1       100.00  100  1      1        0                    
ch4_swptr  1        0         1       100.00  100  1      1        0                    
ch5_csr    1        0         1       100.00  100  1      1        0                    
ch5_sz     1        0         1       100.00  100  1      1        0                    
ch5_a0     1        0         1       100.00  100  1      1        0                    
ch5_am0    1        0         1       100.00  100  1      1        0                    
ch5_a1     1        0         1       100.00  100  1      1        0                    
ch5_am1    1        0         1       100.00  100  1      1        0                    
ch5_desc   1        0         1       100.00  100  1      1        0                    
ch5_swptr  1        0         1       100.00  100  1      1        0                    
ch6_csr    1        0         1       100.00  100  1      1        0                    
ch6_sz     1        0         1       100.00  100  1      1        0                    
ch6_a0     1        0         1       100.00  100  1      1        0                    
ch6_am0    1        0         1       100.00  100  1      1        0                    
ch6_a1     1        0         1       100.00  100  1      1        0                    
ch6_am1    1        0         1       100.00  100  1      1        0                    
ch6_desc   1        0         1       100.00  100  1      1        0                    
ch6_swptr  1        0         1       100.00  100  1      1        0                    
ch7_csr    1        0         1       100.00  100  1      1        0                    
ch7_sz     1        0         1       100.00  100  1      1        0                    
ch7_a0     1        0         1       100.00  100  1      1        0                    
ch7_am0    1        0         1       100.00  100  1      1        0                    
ch7_a1     1        0         1       100.00  100  1      1        0                    
ch7_am1    1        0         1       100.00  100  1      1        0                    
ch7_desc   1        0         1       100.00  100  1      1        0                    
ch7_swptr  1        0         1       100.00  100  1      1        0                    
ch8_csr    1        0         1       100.00  100  1      1        0                    
ch8_sz     1        0         1       100.00  100  1      1        0                    
ch8_a0     1        0         1       100.00  100  1      1        0                    
ch8_am0    1        0         1       100.00  100  1      1        0                    
ch8_a1     1        0         1       100.00  100  1      1        0                    
ch8_am1    1        0         1       100.00  100  1      1        0                    
ch8_desc   1        0         1       100.00  100  1      1        0                    
ch8_swptr  1        0         1       100.00  100  1      1        0                    
ch9_csr    1        0         1       100.00  100  1      1        0                    
ch9_sz     1        0         1       100.00  100  1      1        0                    
ch9_a0     1        0         1       100.00  100  1      1        0                    
ch9_am0    1        0         1       100.00  100  1      1        0                    
ch9_a1     1        0         1       100.00  100  1      1        0                    
ch9_am1    1        0         1       100.00  100  1      1        0                    
ch9_desc   1        0         1       100.00  100  1      1        0                    
ch9_swptr  1        0         1       100.00  100  1      1        0                    
ch10_csr   1        0         1       100.00  100  1      1        0                    
ch10_sz    1        0         1       100.00  100  1      1        0                    
ch10_a0    1        0         1       100.00  100  1      1        0                    
ch10_am0   1        0         1       100.00  100  1      1        0                    
ch10_a1    1        0         1       100.00  100  1      1        0                    
ch10_am1   1        0         1       100.00  100  1      1        0                    
ch10_desc  1        0         1       100.00  100  1      1        0                    
ch10_swptr 1        0         1       100.00  100  1      1        0                    
ch11_csr   1        0         1       100.00  100  1      1        0                    
ch11_sz    1        0         1       100.00  100  1      1        0                    
ch11_a0    1        0         1       100.00  100  1      1        0                    
ch11_am0   1        0         1       100.00  100  1      1        0                    
ch11_a1    1        0         1       100.00  100  1      1        0                    
ch11_am1   1        0         1       100.00  100  1      1        0                    
ch11_desc  1        0         1       100.00  100  1      1        0                    
ch11_swptr 1        0         1       100.00  100  1      1        0                    
ch12_csr   1        0         1       100.00  100  1      1        0                    
ch12_sz    1        0         1       100.00  100  1      1        0                    
ch12_a0    1        0         1       100.00  100  1      1        0                    
ch12_am0   1        0         1       100.00  100  1      1        0                    
ch12_a1    1        0         1       100.00  100  1      1        0                    
ch12_am1   1        0         1       100.00  100  1      1        0                    
ch12_desc  1        0         1       100.00  100  1      1        0                    
ch12_swptr 1        0         1       100.00  100  1      1        0                    
ch13_csr   1        0         1       100.00  100  1      1        0                    
ch13_sz    1        0         1       100.00  100  1      1        0                    
ch13_a0    1        0         1       100.00  100  1      1        0                    
ch13_am0   1        0         1       100.00  100  1      1        0                    
ch13_a1    1        0         1       100.00  100  1      1        0                    
ch13_am1   1        0         1       100.00  100  1      1        0                    
ch13_desc  1        0         1       100.00  100  1      1        0                    
ch13_swptr 1        0         1       100.00  100  1      1        0                    
ch14_csr   1        0         1       100.00  100  1      1        0                    
ch14_sz    1        0         1       100.00  100  1      1        0                    
ch14_a0    1        0         1       100.00  100  1      1        0                    
ch14_am0   1        0         1       100.00  100  1      1        0                    
ch14_a1    1        0         1       100.00  100  1      1        0                    
ch14_am1   1        0         1       100.00  100  1      1        0                    
ch14_desc  1        0         1       100.00  100  1      1        0                    
ch14_swptr 1        0         1       100.00  100  1      1        0                    
ch15_csr   1        0         1       100.00  100  1      1        0                    
ch15_sz    1        0         1       100.00  100  1      1        0                    
ch15_a0    1        0         1       100.00  100  1      1        0                    
ch15_am0   1        0         1       100.00  100  1      1        0                    
ch15_a1    1        0         1       100.00  100  1      1        0                    
ch15_am1   1        0         1       100.00  100  1      1        0                    
ch15_desc  1        0         1       100.00  100  1      1        0                    
ch15_swptr 1        0         1       100.00  100  1      1        0                    
ch16_csr   1        0         1       100.00  100  1      1        0                    
ch16_sz    1        0         1       100.00  100  1      1        0                    
ch16_a0    1        0         1       100.00  100  1      1        0                    
ch16_am0   1        0         1       100.00  100  1      1        0                    
ch16_a1    1        0         1       100.00  100  1      1        0                    
ch16_am1   1        0         1       100.00  100  1      1        0                    
ch16_desc  1        0         1       100.00  100  1      1        0                    
ch16_swptr 1        0         1       100.00  100  1      1        0                    
ch17_csr   1        0         1       100.00  100  1      1        0                    
ch17_sz    1        0         1       100.00  100  1      1        0                    
ch17_a0    1        0         1       100.00  100  1      1        0                    
ch17_am0   1        0         1       100.00  100  1      1        0                    
ch17_a1    1        0         1       100.00  100  1      1        0                    
ch17_am1   1        0         1       100.00  100  1      1        0                    
ch17_desc  1        0         1       100.00  100  1      1        0                    
ch17_swptr 1        0         1       100.00  100  1      1        0                    
ch18_csr   1        0         1       100.00  100  1      1        0                    
ch18_sz    1        0         1       100.00  100  1      1        0                    
ch18_a0    1        0         1       100.00  100  1      1        0                    
ch18_am0   1        0         1       100.00  100  1      1        0                    
ch18_a1    1        0         1       100.00  100  1      1        0                    
ch18_am1   1        0         1       100.00  100  1      1        0                    
ch18_desc  1        0         1       100.00  100  1      1        0                    
ch18_swptr 1        0         1       100.00  100  1      1        0                    
ch19_csr   1        0         1       100.00  100  1      1        0                    
ch19_sz    1        0         1       100.00  100  1      1        0                    
ch19_a0    1        0         1       100.00  100  1      1        0                    
ch19_am0   1        0         1       100.00  100  1      1        0                    
ch19_a1    1        0         1       100.00  100  1      1        0                    
ch19_am1   1        0         1       100.00  100  1      1        0                    
ch19_desc  1        0         1       100.00  100  1      1        0                    
ch19_swptr 1        0         1       100.00  100  1      1        0                    
ch20_csr   1        0         1       100.00  100  1      1        0                    
ch20_sz    1        0         1       100.00  100  1      1        0                    
ch20_a0    1        0         1       100.00  100  1      1        0                    
ch20_am0   1        0         1       100.00  100  1      1        0                    
ch20_a1    1        0         1       100.00  100  1      1        0                    
ch20_am1   1        0         1       100.00  100  1      1        0                    
ch20_desc  1        0         1       100.00  100  1      1        0                    
ch20_swptr 1        0         1       100.00  100  1      1        0                    
ch21_csr   1        0         1       100.00  100  1      1        0                    
ch21_sz    1        0         1       100.00  100  1      1        0                    
ch21_a0    1        0         1       100.00  100  1      1        0                    
ch21_am0   1        0         1       100.00  100  1      1        0                    
ch21_a1    1        0         1       100.00  100  1      1        0                    
ch21_am1   1        0         1       100.00  100  1      1        0                    
ch21_desc  1        0         1       100.00  100  1      1        0                    
ch21_swptr 1        0         1       100.00  100  1      1        0                    
ch22_csr   1        0         1       100.00  100  1      1        0                    
ch22_sz    1        0         1       100.00  100  1      1        0                    
ch22_a0    1        0         1       100.00  100  1      1        0                    
ch22_am0   1        0         1       100.00  100  1      1        0                    
ch22_a1    1        0         1       100.00  100  1      1        0                    
ch22_am1   1        0         1       100.00  100  1      1        0                    
ch22_desc  1        0         1       100.00  100  1      1        0                    
ch22_swptr 1        0         1       100.00  100  1      1        0                    
ch23_csr   1        0         1       100.00  100  1      1        0                    
ch23_sz    1        0         1       100.00  100  1      1        0                    
ch23_a0    1        0         1       100.00  100  1      1        0                    
ch23_am0   1        0         1       100.00  100  1      1        0                    
ch23_a1    1        0         1       100.00  100  1      1        0                    
ch23_am1   1        0         1       100.00  100  1      1        0                    
ch23_desc  1        0         1       100.00  100  1      1        0                    
ch23_swptr 1        0         1       100.00  100  1      1        0                    
ch24_csr   1        0         1       100.00  100  1      1        0                    
ch24_sz    1        0         1       100.00  100  1      1        0                    
ch24_a0    1        0         1       100.00  100  1      1        0                    
ch24_am0   1        0         1       100.00  100  1      1        0                    
ch24_a1    1        0         1       100.00  100  1      1        0                    
ch24_am1   1        0         1       100.00  100  1      1        0                    
ch24_desc  1        0         1       100.00  100  1      1        0                    
ch24_swptr 1        0         1       100.00  100  1      1        0                    
ch25_csr   1        0         1       100.00  100  1      1        0                    
ch25_sz    1        0         1       100.00  100  1      1        0                    
ch25_a0    1        0         1       100.00  100  1      1        0                    
ch25_am0   1        0         1       100.00  100  1      1        0                    
ch25_a1    1        0         1       100.00  100  1      1        0                    
ch25_am1   1        0         1       100.00  100  1      1        0                    
ch25_desc  1        0         1       100.00  100  1      1        0                    
ch25_swptr 1        0         1       100.00  100  1      1        0                    
ch26_csr   1        0         1       100.00  100  1      1        0                    
ch26_sz    1        0         1       100.00  100  1      1        0                    
ch26_a0    1        0         1       100.00  100  1      1        0                    
ch26_am0   1        0         1       100.00  100  1      1        0                    
ch26_a1    1        0         1       100.00  100  1      1        0                    
ch26_am1   1        0         1       100.00  100  1      1        0                    
ch26_desc  1        0         1       100.00  100  1      1        0                    
ch26_swptr 1        0         1       100.00  100  1      1        0                    
ch27_csr   1        0         1       100.00  100  1      1        0                    
ch27_sz    1        0         1       100.00  100  1      1        0                    
ch27_a0    1        0         1       100.00  100  1      1        0                    
ch27_am0   1        0         1       100.00  100  1      1        0                    
ch27_a1    1        0         1       100.00  100  1      1        0                    
ch27_am1   1        0         1       100.00  100  1      1        0                    
ch27_desc  1        0         1       100.00  100  1      1        0                    
ch27_swptr 1        0         1       100.00  100  1      1        0                    
ch28_csr   1        0         1       100.00  100  1      1        0                    
ch28_sz    1        0         1       100.00  100  1      1        0                    
ch28_a0    1        0         1       100.00  100  1      1        0                    
ch28_am0   1        0         1       100.00  100  1      1        0                    
ch28_a1    1        0         1       100.00  100  1      1        0                    
ch28_am1   1        0         1       100.00  100  1      1        0                    
ch28_desc  1        0         1       100.00  100  1      1        0                    
ch28_swptr 1        0         1       100.00  100  1      1        0                    
ch29_csr   1        0         1       100.00  100  1      1        0                    
ch29_sz    1        0         1       100.00  100  1      1        0                    
ch29_a0    1        0         1       100.00  100  1      1        0                    
ch29_am0   1        0         1       100.00  100  1      1        0                    
ch29_a1    1        0         1       100.00  100  1      1        0                    
ch29_am1   1        0         1       100.00  100  1      1        0                    
ch29_desc  1        0         1       100.00  100  1      1        0                    
ch29_swptr 1        0         1       100.00  100  1      1        0                    
ch30_csr   1        0         1       100.00  100  1      1        0                    
ch30_sz    1        0         1       100.00  100  1      1        0                    
ch30_a0    1        0         1       100.00  100  1      1        0                    
ch30_am0   1        0         1       100.00  100  1      1        0                    
ch30_a1    1        0         1       100.00  100  1      1        0                    
ch30_am1   1        0         1       100.00  100  1      1        0                    
ch30_desc  1        0         1       100.00  100  1      1        0                    
ch30_swptr 1        0         1       100.00  100  1      1        0                    


-------------------------------------------------------------------------------

Summary for Variable CSR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for CSR


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable INT_MASKA


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_MASKA


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_MASKB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_MASKB


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_SRCA


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_SRCA


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable INT_SRCB


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for INT_SRCB


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable CH0_CSR


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for CH0_CSR


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch0_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch0_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch1_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch1_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch2_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch2_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch3_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch3_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch4_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch4_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch5_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch5_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch6_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch6_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch7_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch7_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch8_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch8_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch9_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch9_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch10_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch10_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch11_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch11_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch12_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch12_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch13_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch13_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch14_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch14_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch15_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch15_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch16_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch16_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch17_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch17_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch18_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch18_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch19_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch19_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch20_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch20_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch21_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch21_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch22_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch22_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch23_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch23_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch24_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch24_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch25_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch25_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch26_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch26_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch27_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch27_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch28_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch28_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch29_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch29_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_csr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_csr


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_sz


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_sz


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_a0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_a0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_am0


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_am0


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_a1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_a1


Bins

NAME     COUNT AT LEAST 
accessed 34    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_am1


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_am1


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_desc


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_desc


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


-------------------------------------------------------------------------------

Summary for Variable ch30_swptr


CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
User Defined Bins 1        0         1       100.00  


User Defined Bins for ch30_swptr


Bins

NAME     COUNT AT LEAST 
accessed 33    1        


