	simv  +UVM_TESTNAME=vga_lcd_backdoor_reg_access_test -l vga_lcd_backdoor_reg_access.log
	simv  +UVM_TESTNAME=vga_lcd_bit_bash_single_reg_test_test -l vga_lcd_bit_bash_single_reg_test.log
	simv  +UVM_TESTNAME=vga_lcd_bit_bash_test_test -l vga_lcd_bit_bash_test.log
	simv  +UVM_TESTNAME=vga_lcd_env_base_test_test -l vga_lcd_env_base_test.log
	simv  +UVM_TESTNAME=vga_lcd_env_tb_mod_test -l vga_lcd_env_tb_mod.log
	simv  +UVM_TESTNAME=vga_lcd_env_test_test -l vga_lcd_env_test.log
	simv  +UVM_TESTNAME=vga_lcd_mem_access_test -l vga_lcd_mem_access.log
	simv  +UVM_TESTNAME=vga_lcd_mem_shared_access_test -l vga_lcd_mem_shared_access.log
	simv  +UVM_TESTNAME=vga_lcd_mem_single_access_test -l vga_lcd_mem_single_access.log
	simv  +UVM_TESTNAME=vga_lcd_mem_single_walk_test -l vga_lcd_mem_single_walk.log
	simv  +UVM_TESTNAME=vga_lcd_mem_walk_test -l vga_lcd_mem_walk.log
	simv  +UVM_TESTNAME=vga_lcd_reg_access_test -l vga_lcd_reg_access.log
	simv  +UVM_TESTNAME=vga_lcd_reg_bit_bash_test -l vga_lcd_reg_bit_bash.log
	simv  +UVM_TESTNAME=vga_lcd_reg_hw_reset_test -l vga_lcd_reg_hw_reset.log
	simv  +UVM_TESTNAME=vga_lcd_reg_mem_access_test -l vga_lcd_reg_mem_access.log
	simv  +UVM_TESTNAME=vga_lcd_reg_mem_built_in_test -l vga_lcd_reg_mem_built_in.log
	simv  +UVM_TESTNAME=vga_lcd_reg_mem_hdl_paths_test -l vga_lcd_reg_mem_hdl_paths.log
	simv  +UVM_TESTNAME=vga_lcd_reg_shared_access_test -l vga_lcd_reg_shared_access.log
	simv  +UVM_TESTNAME=vga_lcd_reg_single_access_test -l vga_lcd_reg_single_access.log
	simv  +UVM_TESTNAME=vga_lcd_reg_single_bit_bash_test -l vga_lcd_reg_single_bit_bash.log
