# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_IT8XXX2
	select RISCV_ISA_EXT_F if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
	select HAS_PM
	select ARCH_HAS_CUSTOM_CPU_IDLE
	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
	select SOC_PREP_HOOK

if SOC_SERIES_IT8XXX2

config SOC_IT8XXX2
	select RISCV
	select RISCV_ISA_RV32I
	select RISCV_ISA_EXT_ZICSR
	select RISCV_ISA_EXT_ZIFENCEI
	# Workaround mul instruction bug, see:
	# https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
	select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
	select RISCV_ISA_EXT_A
	select RISCV_ISA_EXT_C
	imply XIP

config SOC_IT8XXX2_REG_SET_V1
	bool
	help
	  This option is selected by a variable of which soc, and will
	  determine the register for the IT81xx2 specification.

config SOC_IT8XXX2_REG_SET_V2
	bool
	help
	  This option is selected by a variable of which soc, and will
	  determine the register for the IT82xx2 specification.

config SOC_IT8XXX2_USBPD_PHY_V1
	bool
	help
	  This option is automatically selected by variant soc and sets
	  the USBPD PHY version.

config SOC_IT8XXX2_USBPD_PHY_V2
	bool
	help
	  This option is automatically selected by variant soc and sets
	  the USBPD PHY version.

config SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
	bool
	help
	  This option indicates GPIO-Q group support and is
	  automatically selected based on the SoC variant.

config SOC_IT81302BX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V1

config SOC_IT81202BX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V1

config SOC_IT81302CX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT81202CX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT81302DX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT81202DX
	select SOC_IT8XXX2_REG_SET_V1
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82202AX
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82302AX
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82002AW
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82002BW
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82202BW
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82302BW
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_USBPD_PHY_V2

config SOC_IT82000BW
	select SOC_IT8XXX2_REG_SET_V2
	select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
	select SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED

config SOC_IT8XXX2_PLL_FLASH_48M
	bool "Flash frequency is 48MHz"
	default y
	select FLASH
	help
	  Change frequency of PLL, CPU, and flash to 48MHz during initialization.

	  Set n to use the default settings.
	  (PLL and CPU run at 48MHz, flash frequency is 16MHz)

config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
	bool "The pins of GPIO group K and L aren't bonding with pad"
	default y
	help
	  On IT81202 (128-pins package), the pins of GPIO group K and L aren't
	  bonding with pad. So we configure these pins as internal pull-down
	  at default to prevent leakage current due to floating.

config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW
	bool "The GPIOH7 isn't bonding with pad and is left floating internally"
	default y
	help
	  On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
	  floating internally. We need to enable internal pull-down for the pin
	  to prevent leakage current, but IT81202/IT81302 doesn't have the
	  capability to pull it down. We can only set it as output low,
	  so we enable output low for it at initialization to prevent leakage.

config SOC_IT8XXX2_CPU_IDLE_GATING
	bool
	help
	  This option determines whether the entering CPU idle mode can be
	  gated by individual drivers. When this option is disabled, CPU idle
	  mode is always permitted.

config SOC_IT8XXX2_EC_BUS_24MHZ
	bool "EC bus is 24MHz"
	help
	  Raise EC bus to 24MHz (default is 8MHz).
	  This reduces read/write EC registers latency by 50%.
	  NOTE: There is limitation to enabling this config on it81xx2 series.
	  The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will
	  be fixed at 400KHz.

config SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
	bool "JTAG debug interface"
	help
	  If enabled, the below five pins are configured as JTAG debug interface:
	  - GPIOA0 -> TCK
	  - GPIOA1 -> TDI
	  - GPIOA4 -> TDO
	  - GPIOA5 -> TMS
	  - GPIOA6 -> TRST
	  Supported I/O voltage is 3.3V.

config SOC_IT8XXX2_LCVCO
	bool "LCVCO calibration"
	depends on SOC_IT8XXX2_INT_32K
	help
	  The LCVCO is a highly precise clock controller used for
	  calibrating the frequency shift of the PLL. Enabling this
	  option allows for supported LCVCO calibration, improving
	  the accuracy of the USB clock.

choice
	prompt "Clock source for PLL reference clock"

config SOC_IT8XXX2_INT_32K
	bool "Use the +/-2.3% internal clock generator"

config SOC_IT8XXX2_EXT_32K
	bool "Use external 32.768 kHz clock source"

endchoice

config ARCH_IRQ_VECTOR_TABLE_ALIGN
	default 4

config SOC_IT8XXX2_USE_ILM
	bool
	default y
	help
	  If enabled, Instruction Local Memory (ILM) will be configured to execute
	  code placed in the .__ram_code section out of RAM. This consumes RAM in
	  blocks of 4 kilobytes, but performance of code in ILM is much more
	  predictable than executing from Flash directly, and some code (such as code
	  that writes to the internal Flash) must execute out of RAM.

config SOC_IT8XXX2_EXCEPTIONS_IN_RAM
	bool "Place exception handling code in RAM"
	default y
	select SOC_IT8XXX2_USE_ILM
	help
	  Place exception handling (ISR entry/exit and related) code in ILM, which
	  has more reliable performance characteristics than executing directly from
	  Flash. This can significantly improve performance when under I-cache
	  pressure.

config SOC_IT8XXX2_LIBRARY_TO_RAM
	bool
	help
	  If this is selected it means that there is a library that needs to be excluded
	  from the text section.

config SOC_IT8XXX2_SWITCH_IN_RAM
	bool "Place switch handling code in RAM"
	select SOC_IT8XXX2_USE_ILM
	select SOC_IT8XXX2_LIBRARY_TO_RAM
	help
	  Place content switching code in ILM for better performance.

config SOC_IT8XXX2_SERIAL_IN_RAM
	bool "Place serial handling code in RAM"
	select SOC_IT8XXX2_USE_ILM
	select SOC_IT8XXX2_LIBRARY_TO_RAM
	help
	  Place serial handling (Include uart_ns16550.c and uart_ite_it8xxx2.c) code
	  in ILM. This can improve performance.

config SOC_IT8XXX2_KERNEL_IN_RAM
	bool "Place kernel handling code in RAM"
	select SOC_IT8XXX2_USE_ILM
	select SOC_IT8XXX2_LIBRARY_TO_RAM
	help
	  Place kernel handling code in ILM. This can significantly improve performance.

config SOC_IT8XXX2_ZEPHYR_IN_RAM
	bool "Place zephyr handling code in RAM"
	select SOC_IT8XXX2_USE_ILM
	select SOC_IT8XXX2_LIBRARY_TO_RAM
	help
	  Place zephyr handling code in ILM. This can significantly improve performance.

config SOC_IT8XXX2_RAM_CODE_NOINLINE
	bool "Force RAM code functions to be non-inlined"
	depends on LTO
	help
	  When enabled, functions marked with __soc_ram_code will use the 'noinline'
	  attribute to ensure they are not inlined by the compiler.
	  This guarantees the function body stays in the RAM code section rather
	  than being merged into callers.

config SOC_IT8XXX2_SHA256_HW_ACCELERATE
	bool "HW SHA256 calculation"
	help
	  IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW.
	  We place SHA256 message, hash and key data (total 512bytes) in RAM.
	  If we enable this config, because HW limits, the sha256 data must place in
	  first 4KB of RAM.

config SOC_IT8XXX2_SHA256_BLOCK_SIZE
	hex
	default 0x500 if SOC_IT8XXX2_REG_SET_V2
	default 0x200

DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash

config SOC_IT8XXX2_FLASH_SIZE_BYTES
	hex
	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH))
	help
	  Total size of writable flash.

config ILM_MAX_SIZE
	int "ILM Size in kB"
	default SRAM_SIZE

endif # SOC_SERIES_IT8XXX2
