# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0

config SOC_LITEX_VEXRISCV
	select RISCV
	select INCLUDE_RESET_VECTOR
	select RISCV_ISA_RV32I
	select RISCV_ISA_EXT_M
	select RISCV_ISA_EXT_ZICSR
	select RISCV_ISA_EXT_ZIFENCEI
	# There are varriants of the Vexriscv without cache, be able to set it
	select CPU_HAS_ICACHE if $(dt_node_int_prop_int,/cpus/cpu@0,i-cache-line-size) > 0
	select CPU_HAS_DCACHE if $(dt_node_int_prop_int,/cpus/cpu@0,d-cache-line-size) > 0
	imply XIP

if SOC_LITEX_VEXRISCV

config LITEX_CSR_DATA_WIDTH
	int "Select Control/Status register width"
	default 32

choice LITEX_CSR_ORDERING
	prompt "Select Control/Status register ordering"
	default LITEX_CSR_ORDERING_BIG

config LITEX_CSR_ORDERING_BIG
	bool "Big-endian ordering"
	help
	  Use big-endian ordering for CSR accesses

config LITEX_CSR_ORDERING_LITTLE
	bool "Little-endian ordering"
	help
	  Use little-endian ordering for CSR accesses
endchoice

endif # SOC_LITEX_VEXRISCV
