# ST Microelectronics STM32N6 MCU series

# Copyright (c) 2024 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_STM32N6X
	select ARM
	select CPU_CORTEX_M55
	select ARM_TRUSTZONE_M
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARMV8_1_M_MVEI
	select ARMV8_1_M_MVEF
	select CPU_CORTEX_M_HAS_DWT
	select HAS_STM32CUBE
	select INIT_ARCH_HW_AT_BOOT
	select SOC_RESET_HOOK
	select SOC_EARLY_INIT_HOOK
	select TRUSTED_EXECUTION_SECURE
	select BUILD_OUTPUT_BIN
	# MPU_GAP_FILLING is default when !USERSPACE, select it in the other case as well.
	select MPU_GAP_FILLING if USERSPACE
	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if USERSPACE && !XIP
	select USE_STM32_HAL_RIF if STM32N6_RIF_OPEN

if SOC_SERIES_STM32N6X

config STM32N6_BOOT_SERIAL
	bool "Serial boot target (USB)"

config STM32N6_NPU
	bool "Neural-ART accelerator (NPU)"
	select RESET
	default y
	depends on DT_HAS_ST_STM32_NPU_ENABLED

config STM32N6_RIF_OPEN
	bool "Configure the RIF with all OPEN access"
	default y
	depends on TRUSTED_EXECUTION_SECURE
	help
	  When this option is enabled, the RIMC of all masters and the RISC of all slaves are
	  configured during SoC initialization. Zephyr running with Secure privileges has full
	  access to all SoC resources.

endif # SOC_SERIES_STM32N6X
