TARGET = embox

ARCH = riscv

PLATFORM = syntacore_scr3

CROSS_COMPILE = riscv64-unknown-elf-

CFLAGS += -g -O0

CFLAGS += -march=rv32imc_zifencei_zicsr -mabi=ilp32
/* with FPU */
//CFLAGS += -march=rv32imc_zifencei_zicsr -mabi=ilp32

LDFLAGS += -melf32lriscv

