Xilinx Video IP Pipeline (VIPP)
-------------------------------

General concept
---------------

Xilinx video IP pipeline processes video streams through one or more Xilinx
video IP cores. Each video IP core is represented as documented in video.txt
and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
node of the VIPP represents as a top level node of the pipeline and defines
mappings between DMAs and the video IP cores.

Required properties:

- compatible: Must be "xlnx,video".

- dmas, dma-names: List of one DMA specifier and identifier string (as defined
  in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
  requires a DMA channel with the identifier string set to "port" followed by
  the port index.

- ports: Video port, using the DT bindings defined in ../video-interfaces.txt.

Optional properties:
- memory-region : phandle to /reserved-memory node.
  If memory is reserved for special use by DMAs then this node
  can be used to refer and use from this reserved memory region.

- xlnx,atomic_streamon: This property is useful for the scenario where some of
  the upstream entities are being shared with multiple video devices (dma
  engines) in the same media pipeline. When set, all entities belonging to
  the media pipeline will get enabled even when any one of the dma engine
  present in the media  pipeline start streaming, otherwise the entities
  get enabled only when all dma engines start streaming.

Required port properties:

- direction: should be either "input" or "output" depending on the direction
  of stream.

Example:

	video_cap {
		compatible = "xlnx,video";
		dmas = <&vdma_1 1>, <&vdma_3 1>;
		dma-names = "port0", "port1";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				direction = "input";
				vcap0_in0: endpoint {
					remote-endpoint = <&scaler0_out>;
				};
			};
			port@1 {
				reg = <1>;
				direction = "input";
				vcap0_in1: endpoint {
					remote-endpoint = <&switch_out1>;
				};
			};
		};
	};

Example using reserved memory:
Reserving from 32bit Shared CMA pool of 512MiB using System RAM:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
/ {
	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		psmem_multimedia: multimedia_cma_mem_region {
			compatible = "shared-dma-pool";
			reg = <0x00 0x40000000 0x00 0x20000000>;
			reusable;
		};
	};
};
...
	video_cap {
		/* ... */
		memory-region = <&psmem_multimedia>;
	};


Reserving from 64bit Shared DMA pool of 1792 MiB using external PL based
DDR memory:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
/ {
	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		plmem_multimedia: multimedia_dma_mem_region {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x48 0x0 0x0 0x70000000>;
		};
	};
};
...
	video_cap {
		/* ... */
		memory-region = <&plmem_multimedia>;
	}
