 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	  neuron_stratixiv_arch_timing.blif	  common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml	  451.38	  vpr	  3.00 GiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  42	  -1	  -1	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  3144372	  42	  35	  119888	  86875	  1	  50816	  3438	  92	  68	  12512	  -1	  neuron3d	  1748.3 MiB	  107.01	  466829	  2934319	  1083146	  1824777	  26396	  3070.7 MiB	  121.42	  1.02	  7.60476	  -72127.1	  -6.60476	  5.56512	  0.18	  0.379505	  0.318093	  43.634	  37.1671	  -1	  -1	  -1	  -1	  -1	  655727	  15	  0	  0	  2.71615e+08	  21708.4	  39.03	  59.6901	  51.5812	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	  neuron_stratixiv_arch_timing.blif	  common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml	  475.99	  vpr	  3.00 GiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  42	  -1	  -1	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  3142992	  42	  35	  119888	  86875	  1	  50882	  3437	  92	  68	  12512	  -1	  neuron3d	  1747.0 MiB	  106.93	  491824	  2959115	  1097287	  1744521	  117307	  3069.3 MiB	  138.63	  1.02	  7.70882	  -73552.4	  -6.70882	  5.31116	  0.19	  0.374383	  0.32362	  46.5434	  39.1779	  -1	  -1	  -1	  -1	  -1	  687615	  23	  0	  0	  2.71615e+08	  21708.4	  47.56	  68.7335	  58.9824	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
 3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	  neuron_stratixiv_arch_timing.blif	  common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml	  468.36	  vpr	  3.00 GiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  42	  -1	  -1	  success	  v8.0.0-11925-ga544f5fea-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2025-01-14T21:35:49	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  3142568	  42	  35	  119888	  86875	  1	  50882	  3437	  92	  68	  12512	  -1	  neuron3d	  1746.6 MiB	  106.94	  498184	  3062823	  1134124	  1468642	  460057	  3068.9 MiB	  137.72	  0.97	  7.864	  -76728.1	  -6.864	  5.39064	  0.16	  0.391075	  0.327661	  48.2954	  40.5989	  -1	  -1	  -1	  -1	  -1	  694746	  16	  0	  0	  2.71615e+08	  21708.4	  40.71	  65.5361	  56.0476	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
