 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_ideal_--route_chan_width_60	  0.45	  vpr	  57.24 MiB	  	  -1	  -1	  0.11	  17180	  1	  0.02	  -1	  -1	  29940	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  58612	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  18.5 MiB	  0.00	  6	  9	  6	  3	  0	  57.2 MiB	  0.00	  0.00	  0.55447	  -0.91031	  -0.55447	  0.55447	  0.00	  1.5247e-05	  1.1202e-05	  9.624e-05	  7.1492e-05	  -1	  -1	  -1	  -1	  -1	  2	  4	  18000	  18000	  14049.7	  1561.07	  0.00	  0.00127575	  0.00118994	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
 timing/k6_N10_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_route_--route_chan_width_60	  0.39	  vpr	  56.88 MiB	  	  -1	  -1	  0.09	  17032	  1	  0.03	  -1	  -1	  30036	  -1	  -1	  1	  2	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  58240	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  18.1 MiB	  0.00	  9	  9	  5	  2	  2	  56.9 MiB	  0.00	  0.00	  0.48631	  -0.91031	  -0.48631	  0.48631	  0.00	  1.0537e-05	  6.296e-06	  8.3071e-05	  6.08e-05	  -1	  -1	  -1	  -1	  -1	  4	  1	  18000	  18000	  15707.9	  1745.32	  0.00	  0.00150177	  0.00144181	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
 timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_ideal_--route_chan_width_60	  35.97	  parmys	  207.63 MiB	  	  -1	  -1	  30.15	  212616	  2	  1.13	  -1	  -1	  54432	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  60376	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.2 MiB	  0.04	  31	  86316	  62145	  3320	  20851	  59.0 MiB	  0.16	  0.00	  1.49664	  -15.0848	  -1.49664	  1.49664	  0.00	  0.000582366	  0.000551804	  0.0478457	  0.0452666	  -1	  -1	  -1	  -1	  -1	  50	  5	  3.042e+06	  2.79e+06	  863192.	  3836.41	  0.01	  0.0571117	  0.0538114	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  154	  9	 
 timing/k6_N10_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_route_--route_chan_width_60	  36.34	  parmys	  207.71 MiB	  	  -1	  -1	  30.19	  212696	  2	  1.10	  -1	  -1	  54416	  -1	  -1	  155	  5	  -1	  -1	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  60324	  5	  156	  191	  347	  1	  163	  316	  15	  15	  225	  clb	  auto	  19.1 MiB	  0.05	  33	  86316	  61936	  3548	  20832	  58.9 MiB	  0.16	  0.00	  1.51877	  -14.6769	  -1.51877	  1.51877	  0.00	  0.000585007	  0.000554303	  0.0481935	  0.0455469	  -1	  -1	  -1	  -1	  -1	  59	  7	  3.042e+06	  2.79e+06	  892591.	  3967.07	  0.01	  0.0592953	  0.0557128	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  153	  10	 
 timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_ideal_--route_chan_width_60	  0.52	  vpr	  62.47 MiB	  	  -1	  -1	  0.15	  17300	  1	  0.02	  -1	  -1	  29876	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  63972	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  23.8 MiB	  0.01	  6	  9	  6	  2	  1	  62.5 MiB	  0.00	  0.00	  0.55247	  -0.90831	  -0.55247	  0.55247	  0.00	  1.5422e-05	  1.1498e-05	  9.4034e-05	  7.1831e-05	  -1	  -1	  -1	  -1	  -1	  2	  2	  53894	  53894	  12370.0	  1374.45	  0.00	  0.00126313	  0.0011948	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	 
 timing/k6_N10_mem32K_40nm.xml	  microbenchmarks/d_flip_flop.v	  common_--clock_modeling_route_--route_chan_width_60	  0.53	  vpr	  62.67 MiB	  	  -1	  -1	  0.13	  17332	  1	  0.02	  -1	  -1	  29940	  -1	  -1	  1	  2	  0	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  64172	  2	  1	  3	  4	  1	  3	  4	  3	  3	  9	  -1	  auto	  23.9 MiB	  0.00	  9	  9	  5	  2	  2	  62.7 MiB	  0.00	  0.00	  0.48631	  -0.90831	  -0.48631	  0.48631	  0.00	  1.628e-05	  1.1326e-05	  0.000100275	  7.4439e-05	  -1	  -1	  -1	  -1	  -1	  8	  1	  53894	  53894	  14028.3	  1558.70	  0.00	  0.001205	  0.00113797	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  0	  3	 
 timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_ideal_--route_chan_width_60	  5.48	  vpr	  69.88 MiB	  	  -1	  -1	  1.69	  25936	  2	  0.13	  -1	  -1	  34044	  -1	  -1	  43	  311	  15	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  71552	  311	  156	  972	  1128	  1	  953	  525	  28	  28	  784	  memory	  auto	  29.3 MiB	  0.44	  8558	  218576	  81176	  126482	  10918	  69.9 MiB	  1.26	  0.02	  3.69209	  -4322.15	  -3.69209	  3.69209	  0.00	  0.00566264	  0.00502374	  0.613073	  0.541373	  -1	  -1	  -1	  -1	  -1	  12402	  10	  4.25198e+07	  1.05374e+07	  2.96205e+06	  3778.13	  0.30	  0.773998	  0.68699	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  15	  938	 
 timing/k6_N10_mem32K_40nm.xml	  verilog/mkPktMerge.v	  common_--clock_modeling_route_--route_chan_width_60	  5.41	  vpr	  69.92 MiB	  	  -1	  -1	  1.65	  25824	  2	  0.13	  -1	  -1	  33856	  -1	  -1	  43	  311	  15	  0	  success	  v8.0.0-11920-g63becbef4-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-12-04T15:29:41	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/release/vtr-verilog-to-routing	  71596	  311	  156	  972	  1128	  1	  953	  525	  28	  28	  784	  memory	  auto	  29.4 MiB	  0.44	  8669	  216459	  73858	  129765	  12836	  69.9 MiB	  1.24	  0.02	  4.41733	  -3555.93	  -4.41733	  4.41733	  0.00	  0.00571027	  0.00506699	  0.606205	  0.532426	  -1	  -1	  -1	  -1	  -1	  12695	  11	  4.25198e+07	  1.05374e+07	  3.02951e+06	  3864.17	  0.32	  0.776322	  0.686334	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  14	  939	 
