 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  ap_mem	  ap_time	  ap_full_legalizer_mem	  ap_full_legalizer_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_global_nets	  num_routed_nets	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  28.10	  vpr	  85.89 MiB	  	  0.23	  16788	  -1	  -1	  2	  0.16	  -1	  -1	  33892	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  87952	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  32.2 MiB	  0.92	  8945	  195453	  67462	  117452	  10539	  83.1 MiB	  1.14	  0.02	  4.24256	  -3535.29	  -4.24256	  4.24256	  3.03	  0.0047266	  0.00420892	  0.495161	  0.440444	  -1	  -1	  -1	  -1	  46	  14258	  14	  4.25198e+07	  9.89071e+06	  2.42825e+06	  3097.26	  14.01	  2.26688	  2.03164	  81963	  495902	  -1	  13674	  12	  2508	  2888	  1039968	  435011	  4.40824	  4.40824	  -4330.54	  -4.40824	  -371.448	  -1.34258	  3.12000e+06	  3979.60	  0.98	  1.97	  0.43	  -1	  -1	  0.98	  0.192689	  0.174884	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  28.61	  vpr	  89.27 MiB	  	  0.19	  16912	  -1	  -1	  2	  0.16	  -1	  -1	  33728	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  91412	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  32.3 MiB	  1.00	  8945	  195453	  67462	  117452	  10539	  83.9 MiB	  1.09	  0.02	  4.24256	  -3535.29	  -4.24256	  4.24256	  3.23	  0.00439673	  0.00387964	  0.464219	  0.409008	  -1	  -1	  -1	  -1	  46	  14278	  13	  4.25198e+07	  9.89071e+06	  2.47848e+06	  3161.33	  14.05	  2.05809	  1.83585	  81963	  509322	  -1	  13687	  11	  2477	  2842	  628309	  183554	  4.6903	  4.6903	  -4253.53	  -4.6903	  -195.104	  -1.3767	  3.17357e+06	  4047.92	  1.31	  2.14	  0.43	  -1	  -1	  1.31	  0.196452	  0.182983	  15	  950	 
 timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml	  verilog/mkPktMerge.v	  common_-start_odin_--clock_modeling_dedicated_network	  28.86	  vpr	  86.38 MiB	  	  0.18	  16924	  -1	  -1	  2	  0.18	  -1	  -1	  33688	  -1	  -1	  31	  311	  15	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  88452	  311	  156	  1019	  1160	  1	  965	  513	  28	  28	  784	  memory	  auto	  32.4 MiB	  0.86	  9287	  195453	  66686	  117509	  11258	  82.3 MiB	  1.11	  0.02	  4.12801	  -3603.7	  -4.12801	  4.12801	  2.98	  0.00506386	  0.00456663	  0.488102	  0.431794	  -1	  -1	  -1	  -1	  46	  15578	  14	  4.25198e+07	  9.89071e+06	  2.42368e+06	  3091.42	  14.99	  2.15465	  1.92472	  81963	  496068	  -1	  14973	  12	  2225	  2503	  1188709	  769601	  5.70473	  5.70473	  -4410.99	  -5.70473	  -1643.75	  -3.31884	  3.11542e+06	  3973.75	  0.91	  2.07	  0.43	  -1	  -1	  0.91	  0.187032	  0.169642	  15	  950	 
