 arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  num_io	  num_LAB	  num_DSP	  num_M9K	  num_M144K	  num_PLL	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  routed_wirelength	  avg_routed_wirelength	  routed_wiresegment	  avg_routed_wiresegment	  total_nets_routed	  total_connections_routed	  total_heap_pushes	  total_heap_pops	  logic_block_area_total	  logic_block_area_used	  routing_area_total	  routing_area_per_tile	  crit_path_route_success_iteration	  num_rr_graph_nodes	  num_rr_graph_edges	  collapsed_nodes	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  create_rr_graph_time	  create_intra_cluster_rr_graph_time	  adding_internal_edges	  route_mem	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  router_lookahead_mem	  tile_lookahead_computation_time	  router_lookahead_computation_time	 
 stratixiv_arch.timing.xml	  ucsb_152_tap_fir_stratixiv_arch_timing.blif	  common	  69.07	  vpr	  1.16 GiB	  	  42	  758	  0	  0	  0	  0	  success	  v8.0.0-11852-g026644d7f-dirty	  release IPO VTR_ASSERT_LEVEL=2	  GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	  2024-11-21T16:04:00	  betzgrp-wintermute.eecg.utoronto.ca	  /home/elgamma8/research/temp/temp2/vtr-verilog-to-routing	  1213468	  13	  29	  26295	  20086	  1	  12439	  800	  39	  29	  1131	  LAB	  auto	  1063.1 MiB	  14.23	  70903	  253216	  51547	  191577	  10092	  1176.3 MiB	  10.33	  0.14	  4.99319	  -5223.26	  -3.99319	  2.64446	  0.01	  0.0393935	  0.0325965	  2.91026	  2.41968	  83183	  6.68835	  19827	  1.59419	  25954	  36248	  10076288	  1815088	  0	  0	  2.05929e+07	  18207.7	  15	  331560	  3499109	  -1	  5.28806	  2.7363	  -5589.94	  -4.28806	  0	  0	  6.16	  -1	  -1	  1176.3 MiB	  4.02	  4.55065	  3.84457	  1176.3 MiB	  -1	  12.94	 
