# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_RA8D2
	select ARM
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select FPU
	select CPU_CORTEX_M_HAS_DWT
	select ARMV8_M_DSP
	select HAS_SWO
	select XIP
	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
	select HAS_RENESAS_RA_FSP
	select HAS_PM
	select SOC_RA_DYNAMIC_INTERRUPT_NUMBER
	select ARM_MPU
	select CPU_RA_HAS_DCACHE_WRITETHROUGH if CPU_CORTEX_M85

config SOC_R7KA8D2KFLCAC_CM85
	select CPU_CORTEX_M85
	select GPIO_RA_HAS_VBTICTLR

config SOC_R7KA8D2KFLCAC_CM33
	select CPU_CORTEX_M33
	select SOC_RA_SECOND_CORE_BUILD

if SOC_SERIES_RA8D2

config RENESAS_PN_ROM_SIZE
	hex
	default 0x100000 if SOC_R7KA8D2KFLCAC
	help
	  Code MRAM and Flash size

config RENESAS_PN_PACKAGE_TYPE
	int
	range 1 3
	default 2 if SOC_R7KA8D2KFLCAC
	help
	  Package type:
	  1 -> AB: LFBGA 224 pins
	  2 -> AC: LFBGA 289 pins
	  3 -> AJ: LFBGA 303 pins

config RENESAS_PN_FEATURE_SET
	hex
	default 0x4a if SOC_R7KA8D2KFLCAC
	help
	  Feature set (Convert the feature set character into its ASCII hex value):
	  - A (0x41): Single Core (CM85 only)
	  - J (0x4a): Dual Core

config RENESAS_PN_NUMBER_OF_CORES
	int
	range 1 2
	default 2 if SOC_R7KA8D2KFLCAC
	help
	  Number of SoC cores

endif # SOC_SERIES_RA8D2
