Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
| Date         : Sun Sep 13 18:31:16 2026
| Host         : DESKTOP-8JFH0O2 running 64-bit major release  (build 9200)
| Command      : report_drc -return_string
| Design       : fm_top
| Device       : xc7z010clg400-2
| Speed File   : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------

Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max checks: <unlimited>
             Checks found: 53
+-----------+----------+-------------------------------------+--------+
| Rule      | Severity | Description                         | Checks |
+-----------+----------+-------------------------------------+--------+
| DPIP-1    | Warning  | Input pipelining                    | 8      |
| DPOP-1    | Warning  | PREG Output pipelining              | 5      |
| DPOP-2    | Warning  | MREG Output pipelining              | 12     |
| REQP-1839 | Warning  | RAMB36 async control check          | 8      |
| REQP-28   | Advisory | enum_USE_MULT_NONE_connects_CEM_GND | 9      |
| REQP-30   | Advisory | enum_MREG_0_connects_CEM_GND        | 9      |
| REQP-165  | Advisory | writefirst                          | 1      |
| REQP-181  | Advisory | writefirst                          | 1      |
+-----------+----------+-------------------------------------+--------+

2. REPORT DETAILS
-----------------
DPIP-1#1 Warning
Input pipelining
DSP core/dsp/encoder/current_l_product0 input core/dsp/encoder/current_l_product0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#2 Warning
Input pipelining
DSP core/dsp/encoder/current_l_product_reg input core/dsp/encoder/current_l_product_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#3 Warning
Input pipelining
DSP core/dsp/encoder/current_r_product0 input core/dsp/encoder/current_r_product0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#4 Warning
Input pipelining
DSP core/dsp/encoder/current_r_product_reg input core/dsp/encoder/current_r_product_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#5 Warning
Input pipelining
DSP core/playout/left_product input core/playout/left_product/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#6 Warning
Input pipelining
DSP core/playout/left_product input core/playout/left_product/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#7 Warning
Input pipelining
DSP core/playout/right_product input core/playout/right_product/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#8 Warning
Input pipelining
DSP core/playout/right_product input core/playout/right_product/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPOP-1#1 Warning
PREG Output pipelining
DSP core/dsp/encoder/current_l_product0 output core/dsp/encoder/current_l_product0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#2 Warning
PREG Output pipelining
DSP core/dsp/encoder/current_r_product0 output core/dsp/encoder/current_r_product0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#3 Warning
PREG Output pipelining
DSP core/dsp/encoder/previous_l_product0 output core/dsp/encoder/previous_l_product0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#4 Warning
PREG Output pipelining
DSP core/dsp/encoder/previous_r_product0 output core/dsp/encoder/previous_r_product0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#5 Warning
PREG Output pipelining
DSP core/dsp/encoder/stereo_product0 output core/dsp/encoder/stereo_product0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-2#1 Warning
MREG Output pipelining
DSP core/dsp/encoder/current_l_product0 multiplier stage core/dsp/encoder/current_l_product0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#2 Warning
MREG Output pipelining
DSP core/dsp/encoder/current_l_product_reg multiplier stage core/dsp/encoder/current_l_product_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#3 Warning
MREG Output pipelining
DSP core/dsp/encoder/current_r_product0 multiplier stage core/dsp/encoder/current_r_product0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#4 Warning
MREG Output pipelining
DSP core/dsp/encoder/current_r_product_reg multiplier stage core/dsp/encoder/current_r_product_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#5 Warning
MREG Output pipelining
DSP core/dsp/encoder/previous_l_product0 multiplier stage core/dsp/encoder/previous_l_product0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#6 Warning
MREG Output pipelining
DSP core/dsp/encoder/previous_l_product_reg multiplier stage core/dsp/encoder/previous_l_product_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#7 Warning
MREG Output pipelining
DSP core/dsp/encoder/previous_r_product0 multiplier stage core/dsp/encoder/previous_r_product0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#8 Warning
MREG Output pipelining
DSP core/dsp/encoder/previous_r_product_reg multiplier stage core/dsp/encoder/previous_r_product_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#9 Warning
MREG Output pipelining
DSP core/dsp/encoder/stereo_product0 multiplier stage core/dsp/encoder/stereo_product0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#10 Warning
MREG Output pipelining
DSP core/dsp/encoder/stereo_product_reg multiplier stage core/dsp/encoder/stereo_product_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#11 Warning
MREG Output pipelining
DSP core/playout/left_product multiplier stage core/playout/left_product/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#12 Warning
MREG Output pipelining
DSP core/playout/right_product multiplier stage core/playout/right_product/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

REQP-1839#1 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENARDEN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (resets/axis_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#2 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/ENBWREN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (resets/tx_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#3 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENARDEN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (resets/axis_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#4 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1/ENBWREN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (resets/tx_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#5 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2/ENARDEN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (resets/axis_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#6 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2/ENBWREN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (resets/tx_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#7 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3/ENARDEN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (resets/axis_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1839#8 Warning
RAMB36 async control check
The RAMB36E1 core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3 has an input control pin core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_3/ENBWREN (net: core/fifo/fifo/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (resets/tx_sync/arststages_ff_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-28#1 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#2 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#3 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#4 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#5 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#6 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#7 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#8 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-28#9 Advisory
enum_USE_MULT_NONE_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 USE_MULT attribute is set to NONE, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#1 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#2 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#3 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/l_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#4 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#5 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#6 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/mpx_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#7 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_op_paths[0].g_combine.i_ext_mult/g_two_col_comb.i_gen_upper_bits/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#8 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[0].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-30#9 Advisory
enum_MREG_0_connects_CEM_GND
core/dsp/r_fir/U0/i_synth/g_polyphase_interpolation.i_polyphase_interpolation/g_semi_parallel_and_smac.g_paths[1].g_madd_array_and_accum.g_accum.i_accum/i_add_accum/g_dsp48.g_dsp48e1.i_dsp48e1: When the DSP48E1 MREG attribute is set to 0, the CEM input pin should be tied to GND to save power.
Related violations: <none>

REQP-165#1 Advisory
writefirst
Synchronous clocking is detected for BRAM (ps/ps_i/axi_dma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_1) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
Related violations: <none>

REQP-181#1 Advisory
writefirst
Synchronous clocking is detected for BRAM (ps/ps_i/axi_dma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
Related violations: <none>
